DS566 Datasheet, PDF (32/38 Pages) Xilinx, Inc – PLBV46 Master

PLBV46 Master (v1.00a)
Single Data Beat Read Operation
Figure Top x-ref 5
0ns
MPLB_Clk
100ns
200ns
300ns
400ns
M_request
M_abort
M_buslock
M_priority[0:1]
M_ABus[0:31]
M_RNW
M_BE[0:7]
M_MSize[0:1]
001
M_size[0:3]
M_type[0:2]
0
M_wrDBus[0:63]
M_wrBurst
M_rdBurst
1
10000002
30
01
0
0
PLB_MaddrAck
PLB_MSsize[0:1]
PLB_MRearbitrate
PLB_MBusy
PLB_RdErr
PLB_MWrErr
PLB_MrdBterm
PLB_MrdDAck
PLB_MrdDbus[0:63]
PLB_MwrBterm
PLB_MWrDAck
01
RD0
IP2Bus_MstRd_Req
IP2Bus_MstRd_Addr[0:31]
IP2Bus_MstRd_Length[0:11]
IP2Bus_MstRd_BE[0:7]
IP2Bus_MstRd_Size[0:3]
IP2Bus_MstRd_Type
IP2Bus_MstRd_Lock
IP2Bus_MstRd_Reset
10000002
002
30
X
Bus2IP_MstRd_CmdAck
Bus2IP_MstRd_Cmplt
Bus2IP_MstRd_Error
Bus2IP_MstRd_Rearbitrate
Bus2IP_MstRd_Timeout
Bus2IP_MstRd_Length_is_Zero
IP2Bus_MstRd_clk
Bus2IP_MstRd_src_rdy_n
Bus2IP_MstRd_src_dsc_n
Bus2IP_MstRd_sof_n
Bus2IP_MstRd_sop_n
Bus2IP_MstRd_eop_n
Bus2IP_MstRd_eof_n
Bus2IP_MstRd_d[0:63]
Bus2IP_MstRd_rem[0:7]
IP2Bus_MstRd_dst_rdy_n
IP2Bus_MstRd_dst_dsc_n
Bus2IP_MstRd_RdCnt[0:8]
000
RD0
30
001
DS566_05_033009
Figure 5: PLBV46 Master Single Data Beat Read Timing
32
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DS566 April 24, 2009
Product Specification