DS566 Datasheet, PDF (23/38 Pages) Xilinx, Inc – PLBV46 Master

PLBV46 Master (v1.00a)
Table 2: PLBV46 Master Design Parameters
Feature/Description
Parameter Name
Allowable Values
4 to 15
Default
Values
Set to
This parameter sets the width
of the Bus2IP_MstWr_WrCnt
bus.
C_WRFIFO_WRCNT_WI
DTH
log2(C_WRFIFO_DEP
TH) +1 for Sync and
SRL FIFO
10
Set to
log2(C_WRFIFO_DEP
TH) for async FIFO
Reserved:
This parameter sets the width
of the
C_WRFIFO_OCCUPAN
CY_WIDTH
1
1
IP2Bus_MstWr_Occupancy
input port.
Read LocalLink FIFO Properties
0 = Read LocalLink
Interface is
This Parameter specifies the
synchronous to PLB
Read LocalLink interface
clocking relationship to the
C_RD_LLINK_IS_ASYN Clock
C
1 = Read LocalLink
0
PLB Bus Clock
Interface is
asynchronous to PLB
Clock
This Parameter specifies the
use of SRL16 based memory
core for the Read FIFO if the
Read LocalLink backend is
synchronous to the Bus
C_USE_SRL_RDFIFO
0 = Read FIFO will use
BRAM memory core
1 = Read FIFO will use
SRL16 based memory
0
Clock.
core
This parameter sets the
depth of the Read FIFO
C_RDFIFO_DEPTH
16 to 16,384
(must be 2^N-1 for
Async fifo; must be 2^N
for Sync FIFO; must be
512
16,32, or 64 for SRL
fifo).
0 to 15
This parameter sets the width
of the Bus2IP_MstRd_RdCnt
bus.
C_RDFIFO_RDCNT_WI
DTH
Set to log2(C_RDFIF
O_DEPTH) +1
10
(See table note 2)
Reserved:
This parameter sets the width _{C_RDFIFO_VACANCY_}
of the
IP2Bus_MstRd_Vacancy
WIDTH
1
1
input port.
VHDL
Type
integer
integer
Integer
Integer
integer
integer
integer
DS566 April 24, 2009
www.xilinx.com
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Product Specification