DS566 Datasheet, PDF (13/38 Pages) Xilinx, Inc – PLBV46 Master

PLBV46 Master (v1.00a)
Table 1: PLBV46 Master I/O Signal Description
Signal Name
Interface Signal Type Init Status
Description
Bus2IP_MstRd_Cmplt
IP Read
Command
Intfc.
Output
Active high signal
asserted for one PLB
Clock period to indicate
that the PLB Bus has
completed the data phase
of the requested read
’0’
transfer or has completed
with an exception. This
signal when asserted is
also an indication to the
User Logic that the
associated status reply is
valid and may be sampled
Bus2IP_MstRd_Error
IP Read
Command
Status
Reply Intfc.
Output
Active high signal
indicating that an error
’0’
has occurred during the
requested Read
transaction.
Bus2IP_MstRd_Rearbitrate
IP Read
Command
Status
Reply Intfc.
Output
This active high signal
indicates that the Master
is attempting to initiate the
’0’
requested read operation
but the PLB Slave device
is responding with a
rearbitrate status.
Bus2IP_MstRd_Cmd_Aborted
IP Read
Command
Status
Reply Intfc.
Output
This active high signal is
only asserted if an invalid
Read request is issued by
’0’
the IP.
An example is the
IP2Bus_MstRd_Length
value for a request is set to
zeros.
Bus2IP_MstRd_Cmd_TImeout
IP Read
Command
Status
Reply Intfc.
Output
This active high signal
indicates that the Master
’0’
has received an address
phase Timeout indication
for the requested read
operation.
Bus2IP_MstRd_Length_is_Zero
IP Read
Command
Status
Reply Intfc.
Output
This active high signal
indicates that the data
transferred during the
Read Operation was
’0’
limited by the
IP2Bus_MstRd_Length
qualifier.
Read LocalLink I/O Signals
DS566 April 24, 2009
www.xilinx.com
13
Product Specification