DS566 Datasheet, PDF (18/38 Pages) Xilinx, Inc – PLBV46 Master

PLBV46 Master (v1.00a)
Table 1: PLBV46 Master I/O Signal Description
Signal Name
Interface Signal Type Init Status
Description
IP2Bus_MstWr_Lock
IP Write
Command
Intfc.
Input
Reserved:
Drive input to logic ’0’.
Write Bus Lock is not
currently supported.
IP2Bus_MstWr_Reset
IP Write
Command
Intfc.
Input
Active high signal
requesting a
reinitialization of the Write
logic and Write FIFO.
Bus2IP_MstWr_CmdAck
IP Write
Command
Intfc.
Output
Active high signal
asserted for one PLB
Clock period to indicate
’0’
that the PLB Bus has
accepted the Write
Command request and
the data phase is being
initiated.
Bus2IP_MstWr_Cmplt
IP Write
Command
Intfc.
Output
Active high signal
asserted for one PLB
Clock period to indicate
that the PLB Bus has
completed the data phase
of the requested Write
’0’
transfer or has completed
with an exception. This
signal when asserted is
also an indication to the
User Logic that the
associated status reply is
valid and may be
sampled.
Bus2IP_MstWr_Error
IP Write
Command
Status
Reply Intfc.
Output
Active high signal
indicating that some type
’0’
of error occurred during
the requested Write
transaction.
Bus2IP_MstWr_Rearbitrate
IP Write
Command
Status
Reply Intfc.
Output
This active high signal
indicates that the Master
is attempting to initiate the
’0’
requested write operation
but the PLB Slave device
is responding with a
rearbitrate status.
Bus2IP_MstWr_Cmd_Aborted
IP Write
Command
Status
Reply Intfc.
Output
This active high signal is
only asserted if an invalid
Write request is issued by
’0’
the IP.
An example is the
IP2Bus_MstWr_Length
value for a request is set to
zeros.
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DS566 April 24, 2009
Product Specification