DS566 Datasheet, PDF (15/38 Pages) Xilinx, Inc – PLBV46 Master

PLBV46 Master (v1.00a)
Table 1: PLBV46 Master I/O Signal Description
Signal Name
Interface Signal Type Init Status
Description
Bus2IP_MstRd_src_rdy_n
IP Read
LocalLink
Intfc.
Output
Active low signal
indicating the PLBV46
Master Read LocalLink
interface has data
available in the Read
FIFO to transfer to the IP
client. A data transfer
’1’
occurs when both the
IP2Bus_MstRd_dst_rdy_
n and the
Bus2IP_MstRd_src_rdy_
n are asserted on the
rising edge of the Read
LocalLink synchronization
clock.
Bus2IP_MstRd_src_dsc_n
IP Read
LocalLink
Intfc.
Output
Active low signal
’1’
indicating that the Write
Controller is discontinuing
the read transfer.
IP2Bus_MstRd_dst_rdy_n
IP Read
LocalLink
Intfc.
Input
Active low signal
indicating to the Write
Controller that the IP client
is ready to accept data. A
data transfer occurs when
both the
IP2Bus_MstRd_dst_rdy_
n and the
Bus2IP_MstRd_src_rdy_
n are asserted on the
rising edge of the Read
LocalLink synchronization
clock.
IP2Bus_MstRd_dst_dsc_n
IP Read
LocalLink
Intfc.
Input
Active low signal
indicating to the Write
Controller that the client IP
is discontinuing the
LocalLink Read transfer.
Bus2IP_MstRd_RdCnt(0 :
C_RDFIFO_RDCNT_WIDTH-1)
IP Read
LocalLink
Intfc.
Output
All ’0’
This bus reflects the
number of words that are
loaded in the Write FIFO.
It is synchronous to the
Read LocalLink
synchronization clock.
This bus may be used by
the User IP to monitor the
Read FIFO occupancy.
DS566 April 24, 2009
www.xilinx.com
15
Product Specification