GC5018_06 Datasheet, PDF (95/134 Pages) Texas Instruments – 8-CHANNEL WIDEBAND RECEIVER

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4.4.4.47 RAGC3_CONFIG1 Register
GC5018
8-CHANNEL WIDEBAND RECEIVER
SLWS169A – MAY 2005 – REVISED NOVEMBER 2005
Register name: RAGC3_CONFIG1
BIT 15
0
BIT 7
0
0
err_shift_3(2:0)
0
acc_offset_3(5:0)
0
0
0
0
Page: 0x1860 Address: 0x2E
0
0
delay_adj_3(4:0)
0
0
BIT 8
err_shift_3(4:3)
0
0
BIT 0
0
0
acc_offset_3(5:0) : Constant subtracted from the integrated power measurement result before the error
lookup table
err_shift_3(4:0) : Controls the loop gain by left shifting the error output. Larger values result in higher
gain.
delay_adj_3(4:0) : Sets the delay difference, in samples, between the DVGA outputs and the value
applied to the sample multiplier.
4.4.4.48 RAGC3_SD_THRESH Register
Register name: RAGC3_SD_THRESH
BIT 15
0
0
0
BIT 7
0
0
0
Page: 0x1860 Address: 0x2F
sd_thresh_3(15:8)
0
0
0
0
sd_thresh_3(7:0)
0
0
0
0
BIT 8
0
BIT 0
0
sd_thresh_3(15:0) : This is the threshold used by the Signal Detect block to determine if there is signal
on the inputs. The comparison is done to the output of the squarer block, which is a 32 bit
word. Because of this, these bits are aligned with bits 24 down to 8 of the 32 bit squared
value.
4.4.4.49 RAGC3_SD_TIMER Register
Register name: RAGC3_SD_TIMER
BIT 15
0
0
0
BIT 7
0
0
0
Page: 0x1860 Address: :
0x30
BIT 8
sd_timer_3(15:8)
0
0
0
0
0
BIT 0
sd_timer_3(7:0)
0
0
0
0
0
sd_timer_3(15:0) : After the first no signal sample occurs, this is the amount of samples that control the
length of time to determine the loss of signal condition.
GC5018 GENERAL CONTROL
95