GC5018_06 Datasheet, PDF (14/134 Pages) Texas Instruments – 8-CHANNEL WIDEBAND RECEIVER

GC5018
8-CHANNEL WIDEBAND RECEIVER
SLWS169A – MAY 2005 – REVISED NOVEMBER 2005
DDC0
zeros
pfir output
cfir output
tadjchannel A
tadjchannel B
ncosin
ncocos
cicoutput
mixer i * cos & i * sin
mixer q * cos & q * sin
ddc mux channel A
ddc mux channel B
DDC1
MUX
ddc_tst_sel(5:0)
DDC2
DDC3
DDC4
DDC5
DDC6
DDC7
Receive Interface
rxin_a & rxin_b FIFO outputs
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MUX
tst_select(3:0)
DECIMATE (35:20)
tst_decim17 (19:18)
tst_decim_delay (17:2)
(1:0)
tst_clk
tst_aflag
tst_sync
rxin_d(15:0)
dvga_c(3:2)
rxin_c(15:0)
dvga_c(5:4)
dvga_c(1)
dvga_d(5)
dvga_c(0)
sync
Figure 3-11. Test Bus Output Circuit Showing Options for Selecting Signal
VARIABLE
ssel_tst_decim(2:0)
tst_decim_delay(3:0)
tst_decim17
tst_on
tst_select(3:0)
ddc_tst_sel(5:0)
tst_rate_sel(4:0)
PROGRAMMING
DESCRIPTION
Selects the sync source for the testbus decimator
Sets the testbus decimator delay from sync
When set the decimation factor of the test bus output block is 17X. When cleared, the decimation factor
is 1X (no decimation).
Enables the test bus; rxin_c(15:0) and rxin_d(15:0) are changed from inputs to outputs, dvga_c(5:0) and
dvga_d(5) are used as part of the test bus.
Selects the source block for the testbus output; DDC0-7 or Receive Interface.
Selects the signal to be output from the DDC block
Sets the testbus output clock tst_clk period to (tst_rate_sel + 1) rxclk cycles.
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RECEIVE DIGITAL SIGNAL PROCESSING