GC5018_06 Datasheet, PDF (9/134 Pages) Texas Instruments – 8-CHANNEL WIDEBAND RECEIVER

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Samples
from
ADC FIFO
16
− 17
+
GC5018
8-CHANNEL WIDEBAND RECEIVER
SLWS169A – MAY 2005 – REVISED NOVEMBER 2005
32
hp_corner
3
16
shift
&
limit
VARIABLE
ragc_bypass_X
hp_ena_X
hp_corner_X(2:0)
integ_interval_X(23:0)
acc_shift_X(4:0)
acc_offset_X(5:0)
ragc_sync_delay_X(7:0)
ssel_ragc_interval_X(2:0)
ssel_ragc_freeze_X(2:0)
ssel_ragc_clear_X(2:0)
ragc_freeze_X
ragc_clear_X
ragc_update_X(7:0)
sd_ena_X
sd_thresh_X(15:0)
sd_samples_X(15:0)
sd _timer_X(15:0)
clip_hi_thresh_X(15:0)
clip_lo_thresh_X(15:0)
clip_hi_samples_X(7:0)
clip_lo_samples_X(7:0)
clip_hi_timer_X(15:0)
clip_lo_timer_X(15:0)
clip_error_X(15:0)
ragc_error_map_X
dvga_map_X
gain_map_X
delay_adj_X(4:0)
err_shift_X(4:0)
hp_ena
17
limit
16
Samples to
X ² block
Figure 3-6. High Pass Filter in Receive Input AGC
PROGRAMMING
DESCRIPTION
Bypasses the entire receive AGC circuit when set. X = {0,1,2,3}
Enables high pass filter when set
Adjusts the corner frequency of the high pass filter
Integrate and dump signal power measurement interval in samples.
Shift down amount following the integrate and dump accumulator.
Offset value applied to the shifted integrate and dump output.
AGC sync delay interval, from 1 to 256 samples.
Sync source selection for the interval timer.
Sync source selection for AGC freeze
Sync source selection for the AGC loop accumulator clear
Register bit to freeze the AGC when set
Register bit to clear the AGC accumulator when set
Sets the number of updates per sync event, after which no further updates will occur until the next sync
event. Program to 0x00 to continually update.
Enables freezing the AGC with the signal detector when set
Signal detection threshold for AGC channel X. This 16 bit word is lined up with bits 23 down to 8 of the
square output. The smallest signal level is that can be programmed is therefore 16 LSBs on the ADC
input, and the largest is 4095 LSBs at the ADC input.
The number of samples below the signal detect threshold within the signal detect sample timer window
required to freeze on the AGC.
Window timer to qualify signal detection.
Clip detector high threshold
Clip detector low threshold
A clip event is detected when this number of samples above the clip high threshold within the clip high
sample timer window exceeds this value.
A clip event ends when this number of samples below the clip low threshold within the clip low sample
timer window exceeds this value.
Window timer to qualify clip events.
Window timer to determine when the clip event ends.
Error signal applied to the AGC accumulator when a clip event is active. This data is MSB aligned, and
therefore can cause immediate changes to the accumulator.
128w x 8b memory holding the log to error look up table.
64w x 6b memory holding the accumulator to DVGA look up table
64w x 16b memory holding the accumulator to GAIN look up table (256 decibels is unity gain).
Delay between DVGA output updates and gain map updates to compensate for ADC pipeline delays,
etc.
Error map table output shift up before adding to loop accumulator
RECEIVE DIGITAL SIGNAL PROCESSING
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