GC5018_06 Datasheet, PDF (28/134 Pages) Texas Instruments – 8-CHANNEL WIDEBAND RECEIVER

GC5018
8-CHANNEL WIDEBAND RECEIVER
SLWS169A – MAY 2005 – REVISED NOVEMBER 2005
Step
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
Address
a[5:0]
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x21
0x00
0x01
Data
d[15:0]
0x08B5
0x0B00
0x066D
0xFFC6
0xFB75
0xFB24
0xFDA4
0x008D
0x0213
0x01DC
0x00B3
0xFFA5
0xFF40
0xFF73
0xFFDB
0x0021
0x002E
0x0019
0x0003
0xFFFB
0xFFFC
0x0000
0x0000
0x0000
0x0500
0x8EE0
0x2000
Description
Upper 16 bits of coefficient 37
Upper 16 bits of coefficient 38
Upper 16 bits of coefficient 39
Upper 16 bits of coefficient 40
Upper 16 bits of coefficient 41
Upper 16 bits of coefficient 42
Upper 16 bits of coefficient 43
Upper 16 bits of coefficient 44
Upper 16 bits of coefficient 45
Upper 16 bits of coefficient 46
Upper 16 bits of coefficient 47
Upper 16 bits of coefficient 48
Upper 16 bits of coefficient 49
Upper 16 bits of coefficient 50
Upper 16 bits of coefficient 51
Upper 16 bits of coefficient 52
Upper 16 bits of coefficient 53
Upper 16 bits of coefficient 54
Upper 16 bits of coefficient 55
Upper 16 bits of coefficient 56
Upper 16 bits of coefficient 57
Upper 16 bits of unused coefficient RAM location
Upper 16 bits of unused coefficient RAM location
Upper 16 bits of unused coefficient RAM location
Page register for DDC2 control registers 0-31
DDC2 FIR_MODE register; cdma_mode enabled, 60 tap PFIR, 58 tap CFIR
DDC2 PFIR gain = sum(taps)x2^–18 and CFIR gain = sum(taps)x2^–19
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PROGRAMMING
VARIABLE
DESCRIPTION
crastarttap_cfir(4:0)
Number of DDC CFIR filter taps is 2x(crastarttap + 1)
mpu_ram_read
What set, the PFIR and CFIR coefficient rams are readable via the MPU control interface. The GC5018 signal
path is not operational when this bit is set, it is intended for debug purposes only.
cfir_gain
0 = 2e^–19, 1 = 2e^–18
The CFIR filter’s 18 bit coefficients are loaded in two 32 word memories.
Note: CFIR filter coefficients are shared between A and B channels of a DDC block in CDMA mode.
3.2.8 DDC Programmable FIR Filter (PFIR)
The receive programmable FIR filter (PFIR) provides final pulse shaping of the baseband signal data. It
does not perform any decimation. Filter coefficient size, input, and output data size is 18 bits. A special
strapped mode can be employed for UMTS where two adjacent DDCs (2k & 2k+1, k=0 to 7) can be
combined to yield a filter with twice the number of coefficients. This means the GC5018 can support 4
UMTS DDC channels with double-length filter coefficients (up to 128 taps).
The filter is organized in four partial filter blocks, each containing a data RAM, a coefficient RAM and a
dual multiplier, a common state machine and output accumulator.
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RECEIVE DIGITAL SIGNAL PROCESSING