GC5018_06 Datasheet, PDF (7/134 Pages) Texas Instruments – 8-CHANNEL WIDEBAND RECEIVER

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VARIABLE
recv_pmeterX (57:0)
recv_pmeterX_sqr_sum(20:0)
recv_pmeterX_sync_delay(8:0)
recv_pmeterX_strt_intrvl(20:0)
ssel_recv_pmeter_X(2:0)
pmeterX_iq
recv_pmeterX_ena
GC5018
8-CHANNEL WIDEBAND RECEIVER
SLWS169A – MAY 2005 – REVISED NOVEMBER 2005
PROGRAMMING
DESCRIPTION
58 bit power measurement result. X= {0,1,2,3}.
21 bit integration (square and sum) period. X= {0,1,2,3}.
Power meter delay sync period. X= {0,1,2,3}.
21 bit measurement interval. X= {0,1,2,3}. The strt_intrvl value must be greater than the sqr_sum value.
Sync source. X= {0,1,2,3}.
Selects complex power measurement input mode when set. X= {0,1,2,3}.
Enables power meter when set. X= {0,1,2,3}.
3.1.3 Receive Input AGC (RAGC)
Input signals from the ADCs can be used to create a front end composite AGC loop when combined with
a digitally controlled variable gain amplifier (DVGA) connected before the ADCs. The AGC system
operates by integrating the square of the ADC samples over a programmable interval and applying a table
driven error signal to a loop integrator based on the squared integration output. The error table maps the
signal power to a user programmed error value. The loop integrator output is used to drive map tables to
control the DVGA output pins and a gain adjustment multiplier. Fast updates can be enabled if desired, to
cause the loop integrator to quickly adjust to interfering signals. The ADC input signals can also be passed
through a high pass filter to remove DC offset before squaring the input.
The programmable error table, integrator mapping tables, and clip thresholds, when combined with the
user programmable interval timers provide a highly flexible AGC function.
enable corner
Samples 16
from
ADC FIFO
HigFhiltpearss
Filter
31
X2
integrate and dump signal power measurement
55
acc_shift
57
lsimhiiftt
&
0
1
7 ^{ac6c_o−ffset}
128w x 8b ram
+
{1l2im7.i.t0}
{127..0}
EMrraopr ⁸
TMaabple
Table
limit
update
sd_thresh
signal detect
mode controls
Signal
Level
Detect
no_signal
freeze control register bit
freeze from sync source
clear control register bit
clear sync source
16
clip_error
Mag
Clip
Detect
16
clip_hi_thresh
clip_low_thresh
16
clip detect controls
err_shift ⁵
error
shift
loop accumulator
32
64w x 22b RAM
6 MSBs DTMMVabaaGlppeA ₆
TGaabilne
TGMMaabaailppne ¹⁶
Table
delay adjust ⁵
16
Delay
to DVGA
pins
to DDC
channels
sync
update
sync
delay
update interval
Figure 3-5. Receive Input AGC
RECEIVE DIGITAL SIGNAL PROCESSING
7