GC5018_06 Datasheet, PDF (21/134 Pages) Texas Instruments – 8-CHANNEL WIDEBAND RECEIVER

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GC5018
8-CHANNEL WIDEBAND RECEIVER
SLWS169A – MAY 2005 – REVISED NOVEMBER 2005
Table 3-1. Examples of Decimation and Sample Rates⁽¹⁾
UMTS
UMTS
UMTS
UMTS
CDMA
CDMA
CDMA
CDMA
TD-SCDMA
TD-SCDMA
TD-SCDMA
TD-SCDMA
TD-SCDMA
Input
Sample
Rate
(MSPS)
122.88
92.16
76.80
61.44
122.88
78.6432
78.6432
61.44
92.16
81.92
76.80
76.80
61.44
Zeros
Added
0
0
1
1
rxclk(MHz) and
Zero Pad
Output Rate
(MSPS)
122.88
92.16
153.6
122.88
0
122.88
0
78.6432
1
157.2864
1
122.88
0
92.16
0
81.92
0
76.80
1
153.6
1
122.88
CIC
Decimation
8
6
10
8
25
16
32
25
18
16
15
30
24
CIC
Output
Rate
(MSPS)
15.36
15.36
15.36
15.36
4.9152
4.9152
4.9152
4.9152
5.12
5.12
5.12
5.12
5.12
CFIR
Decimation
2
2
2
2
2
2
2
2
2
2
2
2
2
CFIR
Output
Rate
(MSPS)
7.68
7.68
7.68
7.68
PFIR
Decimation
1
1
1
1
2.4576
1
2.4576
1
2.4576
1
2.4576
1
2.56
1
2.56
1
2.56
1
2.56
1
2.56
1
PFIR
Output
Rate
(MSPS)
7.68
7.68
7.68
7.68
2.4576
2.4576
2.4576
2.4576
2.56
2.56
2.56
2.56
2.56
Output
Decimation
1
1
1
1
1
1
1
1
2
2
2
2
2
(1) The DDC output interfaces, both serial and parallel formats, can be programmed to decimate by 2. For the TD-SCDMA examples listed
above, the DDC output rate is 1.28Msps (1x chip rate).
3.2.5 DDC Channel Delay Adjust and Zero Insertion
interpolation
3
(number of zeros stuffed between samples)
input rate I 18
samples
Mixer
from
Q
18
Delay Memory ¹⁸
I:8 slots x 18−bits ₁₈
Q:8 slots x 18−bits
18
Zero
Pad ¹⁸
I full rxclk rate
Q
samples to
CIC Filter
read offset 3
sync (offset registers)
sync (zero stuff moment)
insert offset 3
Figure 3-22. DDC Delay and Zero Insertion Block
The Receive Channel Delay Adjust function is used to add programmable delays in the channel
downconvert path. Adjusting channel delay can be used to compensate for analog elements external to
the GC5018 digital downconversion such as cables, splitters, analog downconverters, filters, etc.
The Delay Memory block consists of an 8 register memory and a state machine. The state machine uses
a counter to control the write (input) pointer, and the programmed read offset register data to create a
read (output) pointer. Programming larger read offset register values increases the effective delay at a
resolution equal to the input sample rate.
The Zero Pad block is used in conjunction with the Delay Memory for delay adjustments. For example,
with input rates of rxclk/8, the Zero Pad block interpolates the input data to rxclk by inserting 7 zeros. The
Zero Pad’s sync insert offset 3-bit control specifies when the zeros are inserted relative to the Sync signal.
This permits a fine adjustment at the rxclk resolution.
RECEIVE DIGITAL SIGNAL PROCESSING
21