GC5018_06 Datasheet, PDF (63/134 Pages) Texas Instruments – 8-CHANNEL WIDEBAND RECEIVER

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4.4.3.5 RECV_CONFIG0 Register
GC5018
8-CHANNEL WIDEBAND RECEIVER
SLWS169A – MAY 2005 – REVISED NOVEMBER 2005
Register name: RECV_CONFIG0
BIT 15
rate_sel(1:0)
adc_
fifo_strap_ab
0
0
0
BIT 7
0
tst_decim_delay(3:0)
0
0
Page: 0x1800
adc_
fifo_strap_cd
0
self_test_
const_ena
0
Address: 0x04
adc_
fifo_bypass
0
ragc_mpu_ram
_read
0
BIT 8
tst_ decim17
0
BIT 0
pmeter3_iq
pmeter2_iq
pmeter1_iq
pmeter0_iq
0
0
0
0
0
rate_sel(1:0) : Tells the RECV_CDRV the input rate. This is the rxin_a/b/c/d input rate and the rate that
the RECEIVE INPUT INTERFACE block sends data to the DDCs.
rate_sel
Input clock rate
00
rxclk
01
rxclk/2
10
rxclk/4
11
rxclk/8
adc_fifo_strap_ab : When asserted, the input pointers of the rxin_a FIFO and rxin_b FIFO are hooked
together in lock step configuration. This is used for maintaining FIFO delay consistency when
complex inputs are driven on rxin_a(I) and rxin_b(Q). rxin_a is the Master.
adc_fifo_strap_cd : When asserted, the input pointers of the rxin_c FIFO and rxin_d FIFO are hooked
together in lock step configuration. This is used for maintaining FIFO delay consistency when
complex inputs are driven on rxin_c(I) and rxin_d(Q). rxin_c is the Master.
self_test_const_ena : When asserted, (with slf_tst_ena also asserted), a constant value is output by the
test and noise generator instead of the pseudo random sequence. The constant value is
programmable.
adc_fifo_bypass : When asserted, the ADC FIFO circuits are bypassed. Input data is then clocked in
directly using the rxclk input. The ssel_ddc selection value will control the location of the
internally generated sample clock when this bit is asserted where rate_sel is rxclk/2, rxclk/4
or rxclk/8.
ragc_mpu_ram_read : When asserted, the RAMs in the RAGC blocks can be read. This bit should only
be set when reading the RAGC map rams via the mpu interface and must be cleared for
proper RAGC operation.
tst_decim17 : When set, the decimation factor of the tst_decimator block is 17X. When cleared, the
decimation factor is 1X (no decimation).
tst_decim_delay(3:0) : These bits set the delay from the sync occurring until the decimator samples. In
other words, the moment of the decimator is set by this delay value.
pmeter3_iq : When asserted, the pmeter3 block takes input from both rxin_c and rxin_d as a complex
sample pair. When de-asserted, only input from rxin_d is used for the power measurement.
pmeter2_iq : When asserted, the pmeter2 block takes input from both rxin_c and rxin_d as a complex
sample pair. When de-asserted, only input from rxin_c is used for the power measurement.
pmeter1_iq : When asserted, the pmeter1 block takes input from both rxin_a and rxin_b as a complex
sample pair. When de-asserted, only input from rxin_b is used for the power measurement.
pmeter0_iq : When asserted, the pmeter0 block takes input from both rxin_a and rxin_b as a complex
sample pair. When de-asserted, only input from rxin_a is used for the power measurement.
GC5018 GENERAL CONTROL
63