GC5018_06 Datasheet, PDF (25/134 Pages) Texas Instruments – 8-CHANNEL WIDEBAND RECEIVER

www.ti.com
GC5018
8-CHANNEL WIDEBAND RECEIVER
SLWS169A – MAY 2005 – REVISED NOVEMBER 2005
A single set of programmed tap values are used for both the A-side and B-side DDC channels (two CDMA
channels) within a single DDC block when in CDMA mode.
After the CFIR filter performs the convolution, gain is applied at full precision, the signal is rounded, and
then hard limited. A shifter at the output of the filter then scales the data by either 2e-19 or 2e-18. The
gain through the filter is therefore:
Sum(CFIR coefficients) x 2 ^{–(18 or 19)}
Coefficients are organized in two groups of 32 words, each 18 bits wide. For fully utilized filters, the 64
coefficients are loaded 0 through 31 into the first RAM, and 32 through 63 into the second RAM. The 16
bit MSBs and 2 bit LSBs are written into the RAMs using different page register values. Shorter filters
require the coefficients be loaded into the 2 rams equally, starting from address 0.
For example, a CFIR coefficient set for a symmetric 58 tap TD-SCDMA CFIR is:
Taps
0 = 57
1 = 56
2 = 55
3 = 54
4 = 53
5 = 52
6 = 51
7 = 50
8 = 49
9 = 48
10 = 47
11 = 46
12 = 45
13 = 44
14 = 43
Coefficient
–13
–20
14
101
184
133
–147
–562
–768
–364
719
1905
2126
567
–2416
Taps
15 = 42
16 = 41
17 = 40
18 = 39
19 = 38
20 = 37
21 = 36
22 = 35
23 = 34
24 = 33
25 = 32
26 = 31
27 = 30
28 = 29
Coefficient
–4975
–4649
–232
6581
11266
8917
–1957
–16736
–25469
– 17599
11560
56455
102215
131071
The first 29 coefficients are loaded into addresses 0 through 28 in the first coefficient RAM, and the
remaining 29 are loaded into addresses 0 through 28 in the second coefficient RAM. Loading the 18 bit
coefficients requires 2 writes per coefficient, one for the upper 16 bits and another for the lower 2 bits.
To program this coefficient set for the DDC2 CFIR, the following control microprocessor interface
sequence would be used.
Step
1
2
3
4
5
6
7
8
9
10
11
12
Address
a[5:0]
0x21
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
Data
d[15:0]
0x0480
0x0003
0x0000
0x0002
0x0001
0x0000
0x0001
0x0001
0x0002
0x0000
0x0000
0x0003
Description
Page register for DDC2 CFIR Coefficient RAM 0-31, LSBs.
2 lower bits of coefficient 0
2 lower bits of coefficient 1
2 lower bits of coefficient 2
2 lower bits of coefficient 3
2 lower bits of coefficient 4
2 lower bits of coefficient 5
2 lower bits of coefficient 6
2 lower bits of coefficient 7
2 lower bits of coefficient 8
2 lower bits of coefficient 9
2 lower bits of coefficient 10
RECEIVE DIGITAL SIGNAL PROCESSING
25