GC5018_06 Datasheet, PDF (30/134 Pages) Texas Instruments – 8-CHANNEL WIDEBAND RECEIVER

GC5018
8-CHANNEL WIDEBAND RECEIVER
SLWS169A – MAY 2005 – REVISED NOVEMBER 2005
www.ti.com
Mode
UMTS
UMTS
UMTS
UMTS
CDMA
CDMA
CDMA
CDMA
CDMA
CDMA
rxclk
(MHz)
153.60
122.88
153.60
122.88
157.2864
122.88
78.6432
153.60
81.92
76.80
CIC
DECIMATIO
N
10
8
10
8
32
25
16
30
16
15
PFIR
MAX LENGTH
64
64
128
128
64
64
64
64
64
60
PFIR
MIN LENGTH
32
32
64
64
32
32
32
32
32
32
COMMENTS
UMTS, 1 to 6 DDC channels
UMTS, 1 to 6 DDC channels
Strapped UMTS double length PFIR configuration; 1, 2 or 3 DDC
channels.
Strapped UMTS double length PFIR configuration; 1, 2 or 3 DDC
channels
CDMA2000
CDMA2000
CDMA2000 low power configuration
TD-SCDMA
TD-SCDMA
TD-SCDMA low power configuration
Coefficients are organized in four groups of 16 words, each 18 bits wide. For fully utilized filters, the 64
coefficients are loaded 0 through 31 into the first and second RAMs, and 32 through 63 into the third and
fourth RAMs. The 16 bit MSBs and 2 bit LSBs are written into the RAMs using different page register
values. Shorter filters require the coefficients be loaded into the 4 rams equally, starting from address 0
and address 16.
For example, a CFIR coefficient set for a symmetric 60 tap TD-SCDMA PFIR is:
Taps
0 = 59
1 = 58
2 = 57
3 = 56
4 = 55
5 = 54
6 = 53
7 = 52
8 = 51
9 = 50
10 = 49
11 = 48
12 = 47
13 = 46
14 = 45
Coefficient
–2
1
4
–8
–2
21
–13
–28
46
1
–85
96
82
–266
38
Taps
15 = 44
16 = 43
17 = 42
18 = 41
19 = 40
20 = 39
21 = 38
22 = 37
23 = 36
24 = 35
25 = 34
26 = 33
27 = 32
28 = 31
29 = 30
Coefficient
420
–331
–319
744
–440
–1005
2389
514
–6182
1845
12959
–8691
–27246
34166
131071
The first 15 coefficients are loaded into addresses 0 through 14 in the first coefficient RAM, the second
group of 15 are loaded into addresses 16 through 30 corresponding to the second coefficient RAM, the
third group of 15 are loaded into the third coefficient ram at addresses 0 through 14, and the fourth group
of 15 are loaded into addresses 16 through 30 in the fourth coefficient RAM. Loading the 18 bit
coefficients requires 2 writes per coefficient, one for the upper 16 bits and another for the lower 2 bits.
To program this coefficient set for the DDC2 PFIR, the following control microprocessor interface
sequence would be used.
30
RECEIVE DIGITAL SIGNAL PROCESSING