GC5018_06 Datasheet, PDF (106/134 Pages) Texas Instruments – 8-CHANNEL WIDEBAND RECEIVER

GC5018
8-CHANNEL WIDEBAND RECEIVER
SLWS169A – MAY 2005 – REVISED NOVEMBER 2005
4.4.5.12 PHASEADD1B Register
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Register name: PHASEADD1B
BIT 15
0
0
Page: 0x0%00
where:
% = 2×(DDC channel #)+1
Address: 0x0B DOUBLE BUFFERED, REQUIRES SYNC FOR
LOADING
BIT 8
phase_add_b(31:24)
0
0
0
0
0
0
BIT 7
0
0
phase_add_b(23:16)
0
0
0
0
BIT 0
0
0
phase_add_b(31:16) : This 32 bit word is used to control the frequency of the NCO. This value is added
to the frequency accumulator every clock cycle (B channel in CDMA mode).
4.4.5.13 PHASE_OFFSETA Register
Register name:
PHASE_OFFSETA
BIT 15
0
0
BIT 7
0
0
Page: 0x0%00
where:
% = 2×(DDC channel #)+1
Address: 0x0C DOUBLE BUFFERED, REQUIRES SYNC FOR
LOADING
BIT 8
phase_offset_a(15:8)
0
0
0
0
0
0
phase_offset_a(7:0)
0
0
0
0
BIT 0
0
0
phase_offset_a(15:0) : This is the fixed phase offset added to the output of the frequency accumulator
for sinusoid generation in the NCO. (UMTS mode and A channel in CDMA mode).
4.4.5.14 PHASE_OFFSETB Register
Register name:
PHASE_OFFSETB
BIT 15
0
0
BIT 7
0
0
Page: 0x0%00
where:
% = 2×(DDC channel #)+1
Address: 0x0D DOUBLE BUFFERED, REQUIRES SYNC FOR
LOADING
BIT 8
phase_offset_b(15:8)
0
0
0
0
0
0
phase_offset_b(7:0)
0
0
0
0
BIT 0
0
0
phase_offset_b(15:0) : This is the fixed phase offset added to the output of the frequency accumulator
for sinusoid generation in the NCO. (B channel in CDMA mode)
106 GC5018 GENERAL CONTROL