GC5018_06 Datasheet, PDF (50/134 Pages) Texas Instruments – 8-CHANNEL WIDEBAND RECEIVER

GC5018
8-CHANNEL WIDEBAND RECEIVER
SLWS169A – MAY 2005 – REVISED NOVEMBER 2005
www.ti.com
Page Register
Contents in Hex
0x0900
0x0920
Address
Pin a5
0
0
Registers Addressed With 5 Bit Address Space, Pins (a4:a0)
DDC4 Control Registers 0x00 through 0x1F
DDC4 Control Registers 0x20 through 0x3F
0x0A00
0x0A20
0x0A40
0x0A60
0x0A80
0x0AA0
0x0AC0
0x0AE0
0x0B00
0x0B20
0
DDC5 PFIR taps 0 through 31 coefficient lsbs (1:0)
0
DDC5 PFIR taps 32 through 63 coefficient lsbs (1:0)
0
DDC5 PFIR taps 0 through 31 coefficient msbs (17:2)
0
DDC5 PFIR taps 32 through 63 coefficient msbs (17:2)
0
DDC5 CFIR taps 0 through 31 coefficient lsbs (1:0)
0
DDC5 CFIR taps 32 through 63 coefficient lsbs (1:0)
0
DDC5 CFIR taps 0 through 31 coefficient msbs (17:2)
0
DDC5 CFIR taps 32 through 63 coefficient msbs (17:2)
0
DDC5 Control Registers 0x00 through 0x1F
0
DDC5 Control Registers 0x20 through 0x3F
0x0C00
0x0C20
0x0C40
0x0C60
0x0C80
0x0CA0
0x0CC0
0x0CE0
0x0D00
0x0D20
0
DDC6 PFIR taps 0 through 31 coefficient lsbs (1:0)
0
DDC6 PFIR taps 32 through 63 coefficient lsbs (1:0)
0
DDC6 PFIR taps 0 through 31 coefficient msbs (17:2)
0
DDC6 PFIR taps 32 through 63 coefficient msbs (17:2)
0
DDC6 CFIR taps 0 through 31 coefficient lsbs (1:0)
0
DDC6 CFIR taps 32 through 63 coefficient lsbs (1:0)
0
DDC6 CFIR taps 0 through 31 coefficient msbs (17:2)
0
DDC6 CFIR taps 32 through 63 coefficient msbs (17:2)
0
DDC6 Control Registers 0x00 through 0x1F
0
DDC6 Control Registers 0x20 through 0x3F
0x0E00
0x0E20
0x0E40
0x0E60
0x0E80
0x0EA0
0x0EC0
0x0EE0
0x0F00
0x0F20
0
DDC7 PFIR taps 0 through 31 coefficient lsbs (1:0)
0
DDC7 PFIR taps 32 through 63 coefficient lsbs (1:0)
0
DDC7 PFIR taps 0 through 31 coefficient msbs (17:2)
0
DDC7 PFIR taps 32 through 63 coefficient msbs (17:2)
0
DDC7 CFIR taps 0 through 31 coefficient lsbs (1:0)
0
DDC7 CFIR taps 32 through 63 coefficient lsbs (1:0)
0
DDC7 CFIR taps 0 through 31 coefficient msbs (17:2)
0
DDC7 CFIR taps 32 through 63 coefficient msbs (17:2)
0
DDC7 Control Registers 0x00 through 0x1F
0
DDC7 Control Registers 0x20 through 0x3F
0x1000
0x1020
0x1040
0x1080
0x10A0
0
Receive Input AGC0 Error RAM addresses 0 through 31
0
Receive Input AGC0 Error RAM addresses 32 through 63
0
Receive Input AGC0 DVGA RAM addresses 0 through 31
0
Receive Input AGC0 Gain RAM addresses 0 through 31
0
Receive Input AGC0 Gain RAM addresses 32 through 63
0x1100
0x1120
0x1140
0x1180
0
Receive Input AGC1 Error RAM addresses 0 through 31
0
Receive Input AGC1 Error RAM addresses 32 through 63
0
Receive Input AGC1 DVGA RAM addresses 0 through 31
0
Receive Input AGC1 Gain RAM addresses 0 through 31
50
GC5018 GENERAL CONTROL