GC5018_06 Datasheet, PDF (33/134 Pages) Texas Instruments – 8-CHANNEL WIDEBAND RECEIVER

www.ti.com
Step
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
Address
a[5:0]
0x1D
0x1E
0x1F
0x21
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x21
0x00
0x01
Data
d[15:0]
0x215D
0x7FFF
0x0000
0x0460
0x7FFF
0x215D
0xE564
0xF783
0x0CA7
0x01CD
0xF9F6
0x0080
0x0255
0xFF04
0xFF92
0x00BA
0xFFB0
0xFFAD
0x0069
0x008D
0x0009
0xFFBD
0x0014
0x0018
0xFFEA
0x0000
0x000B
0xFFF9
0xFFFC
0x0005
0xFFFF
0xFFFE
0x0001
0x0000
0xFFFF
0x0000
0x0500
0x8EE0
0x2000
GC5018
8-CHANNEL WIDEBAND RECEIVER
SLWS169A – MAY 2005 – REVISED NOVEMBER 2005
Description
Upper 16 bits of coefficient 28
Upper 16 bits of coefficient 29
Upper 16 bits of unused coefficient RAM location
Page register for DDC2 PFIR Coefficient RAMS 32-47 AND 48-63, MSBs.
Upper 16 bits of coefficient 30
Upper 16 bits of coefficient 31
Upper 16 bits of coefficient 32
Upper 16 bits of coefficient 33
Upper 16 bits of coefficient 34
Upper 16 bits of coefficient 35
Upper 16 bits of coefficient 36
Upper 16 bits of coefficient 37
Upper 16 bits of coefficient 38
Upper 16 bits of coefficient 39
Upper 16 bits of coefficient 40
Upper 16 bits of coefficient 41
Upper 16 bits of coefficient 42
Upper 16 bits of coefficient 43
Upper 16 bits of coefficient 44
Upper 16 bits of unused coefficient RAM location
Upper 16 bits of coefficient 45
Upper 16 bits of coefficient 46
Upper 16 bits of coefficient 47
Upper 16 bits of coefficient 48
Upper 16 bits of coefficient 49
Upper 16 bits of coefficient 50
Upper 16 bits of coefficient 51
Upper 16 bits of coefficient 52
Upper 16 bits of coefficient 53
Upper 16 bits of coefficient 54
Upper 16 bits of coefficient 55
Upper 16 bits of coefficient 56
Upper 16 bits of coefficient 57
Upper 16 bits of coefficient 58
Upper 16 bits of coefficient 59
Upper 16 bits of unused coefficient RAM location
Page register for DDC2 control registers 0-31
DDC2 FIR_MODE register; cdma_mode enabled, 60 tap PFIR, 58 tap CFIR
DDC2 PFIR gain = sum(taps)x2^–18 and CFIR gain = sum(taps)x2^–19
RECEIVE DIGITAL SIGNAL PROCESSING
33