GC5018_06 Datasheet, PDF (79/134 Pages) Texas Instruments – 8-CHANNEL WIDEBAND RECEIVER

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4.4.4.2 RAGC_CONFIG1 Register
GC5018
8-CHANNEL WIDEBAND RECEIVER
SLWS169A – MAY 2005 – REVISED NOVEMBER 2005
Register name: RAGC_CONFIG1
BIT 15
ragc_ freeze_0 ragc_ freeze_1 ragc_ freeze_2
0
0
0
Page: 0x1840
ragc_ freeze_3 ragc_ clear_0
0
0
Address: 0x01
ragc_ clear_1
0
ragc_ clear_2
0
BIT 8
ragc_ clear_3
0
BIT 7
complex01
0
complex23
0
ssel_ragc_interval_0(2:0)
0
0
0
BIT 0
ssel_ragc_interval_1(2:0)
0
0
0
ragc_freeze_X : Freezes the receive AGC block when set.
ragc_clear_X : Clears the loop error accumulator when set.
complex01 : When set, receive AGC 0 uses complex input with the second sample stream coming from
receive AGC 1. The clip detect, high pass, and squarer from receive AGC 1 are used to
generate inputs for receive AGC 0.
complex23 : When set, receive AGC 2 uses complex input with the second sample stream coming from
receive AGC 3. The clip detect, high pass, and squarer from receive AGC 3 are used to
generate inputs for receive AGC 2.
ssel_ragc_interval_0(2:0) : Selects the sync source for receive AGC 0. After a programmed delay from
sync, the interval update timer is started.
ssel_ragc_interval_1(2:0) : Selects the sync source for receive AGC 1. After a programmed delay from
sync, the interval update timer is started.
4.4.4.3 RAGC_CONFIG2 Register
Register name: RAGC_CONFIG2
BIT 15
ssel_ragc_freeze_0(2:0)
0
0
0
Page: 0x1840 Address: 0x02
ssel_ragc_freeze_1(2:0)
0
0
0
BIT 8
ssel_ragc_ freeze_2(2:1)
0
0
BIT 7
ssel_ragc_freez
e_2(0)
0
ssel_ragc_freeze_3(2:0)
0
0
0
unused
0
BIT 0
ssel_ragc_interval_2(2:0)
0
0
0
ssel_ragc_freeze_X(2:0) : Selects the sync source that will freeze the receive AGC loop when asserted.
ssel_ragc_interval_2(2:0) : Selects the sync source for receive AGC 2. After a programmed delay from
sync, the interval update timer is started.
GC5018 GENERAL CONTROL
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