GC5018_06 Datasheet, PDF (44/134 Pages) Texas Instruments – 8-CHANNEL WIDEBAND RECEIVER

GC5018
8-CHANNEL WIDEBAND RECEIVER
SLWS169A – MAY 2005 – REVISED NOVEMBER 2005
www.ti.com
4 GC5018 GENERAL CONTROL
The GC5018 is configured over a bi-directional 16 bit parallel data microprocessor control port. The
control port permits access to the control registers which configure the chip. The control registers are
organized using a paged-access scheme using 6 address lines. Half of the 64 addresses (Address 32
through Address 63) represent global registers. The other 32 (Address 0 through Address 31) are paged
registers. This arrangement permits accessing a large number of control registers using relatively few
address lines.
Global registers (Address 32 through Address 63) are used to read/write GC5018 parameters that are
global in nature and can benefit from single read/write operations. Examples include chip status, reset,
sync options, checksum ramp parameters, interrupt sources, interrupt masks, 3-state controls and the
page register.
Global Address 33 is the page register. Writing a 16 bit value to this register sets the page to which future
write or read operations performed. These paged-registers contain the actual parameters that configure
the chip and are accessed by writing/reading address 0 through address 31.
The global 3-state register can be used to 3-state the output drivers on the GC5018, and also includes the
capability of disabling the chip’s internal rxclk.
VARIABLE
rxclk_ena
3-state(10:0)
arst_func
PROGRAMMING
DESCRIPTION
Enables the internal rxclk when set. When cleared, the GC5018 will ignore the rxclk input signal and
hold the internal clock low.
Various output pins are forced into tristate mode when these bits are asserted. See the GBL_3-STATE
register description for pin groups to bit assignments.
When asserted, the internal datapath is held reset. The control register programming is not affected.
4.1 Microprocessor Interface Control Data, Address, and Strobes
The microprocessor control bus consists of 16 bi-directional control data lines d[15:0], 6 address lines
a[5:0], a read enable line rd_n, a write enable line wr_n, and a chip enable line ce_n. These lines usually
interface to a microprocessor or DSP chip and is intended to look like a block of memory.
The interface can be operated in a 3 pin control mode (using rd_n, wr_n and ce_n) or 2 pin control mode
(using wr_n and ce_n with rd_n always low).
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GC5018 GENERAL CONTROL