GC5018_06 Datasheet, PDF (29/134 Pages) Texas Instruments – 8-CHANNEL WIDEBAND RECEIVER

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MPU control
interface
read data
write data
write pointer
Filter cell 1
COEF
RAM
16x18
mpu
ram_read
MUX
read pointer
complex input
samples from cfir
(or adjacent DDC if
double_tap=”01”)
DATA
RAM
32x36
GC5018
8-CHANNEL WIDEBAND RECEIVER
SLWS169A – MAY 2005 – REVISED NOVEMBER 2005
cell 2
cell 3
cell 4
reg
from adjacent DDC
(if double_tap=”10”)
to adjacent DDC
(if double_tap=“10” )
complex
output
samples
crastarttap
write
pointer
read
pointer
State Machine
Figure 3-25. DDC PFIR Block Diagram
output
sample
valid
The PFIR length is programmable. This permits turning off taps and saving power if short filters are
appropriate. The filter’s output data can be shifted over a range of 0 to 7 bits where it is then rounded and
hard limited to 18 bits. The shift range results in a gain that ranges from 2e^–19 to 2e^–12.
The gain of the PFIR block is: sum(coefficients) × 2^-shift, where shift ranges from 12 to 19.
The maximum PFIR filter length is a function of GC5018 clock rate and output sample rate and is limited
by the number of coefficient memory registers. The maximum number of taps is 64 and the minimum
number is 32 (for both CDMA and UMTS). Lengths between these limits can be specified in increments of
4. For strapped UMTS with double length filters, the range of taps available is 64 to 128 in increments of
8.
Subject to the above minimum and maximum values, the number of maximum taps available is:
UMTS Mode: 4 × (CIC DECIMATION × 2)
Strapped UMTS Mode: 8 × (CIC DECIMATION × 2)
CDMA Mode: 2 × (CIC DECIMATION × 2)
PFIR coefficients and gain shift values are shared between both A and B CDMA channels in a DDC block.
Example PFIR filter lengths available based on mode and rxclk frequency:
RECEIVE DIGITAL SIGNAL PROCESSING
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