GC5018_06 Datasheet, PDF (41/134 Pages) Texas Instruments – 8-CHANNEL WIDEBAND RECEIVER

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GC5018
8-CHANNEL WIDEBAND RECEIVER
SLWS169A – MAY 2005 – REVISED NOVEMBER 2005
Decimation by 2 in the output interface can be achieved by setting the frame strobe interval and clock
divider to 1/2 the PFIR output rate. The serial interface samples the PFIR output each time the transfer
interval defined by these two settings has completed. The decimation moment can be controlled using the
rxsync_X input signal selected as the sync source for the serial interface.
The timing diagram below shows the DDC serial output timing.
tsetup thold
tpd
rxclk
rxsync_X
rxsync_out_X
rxout_X_Y
rxsync_X can be a pulse or level − interface will generate periodic frame strobes using programmed frame sync interval
3 rxclk + 1 Programmed bit time
Programmed bit time
(2 rxclk cycles for this example)
MSB
VARIABLE
pser_recv_fsinvl(6:0)
pser_recv_bits(4:0)
pser_recv_clkdiv(3:0)
pser_recv_8pin
pser_recv_alt
pser_recv_fsdel(1:0)
ssel_serial(2:0)
tristate(6:3)
Figure 3-31. Serial Output Interface Timing Diagram
PROGRAMMING
DESCRIPTION
Frame sync interval in bits
Number of data output bits - 1. i.e.: 10001= 18 bits
Receive serial interface clock divider rate – 1.
0= rcclk, 15= rxclk/16
When set, configures the serial out pins for 4I and 4Q in UMTS mode. When clear, the mode is 2I and
2Q. Used in conjunction with pser_recv_alt.
When set, outputs Q data from adjacent DDC channel.
Number of bit clocks the frame sync is output early with respect to serial data.
Sync source selection, 1 of 8.
Tristate controls for the rx_sync_out_X and rxout_X_X pins. Pins are in tristate when the tristate register
bits are set.
RECEIVE DIGITAL SIGNAL PROCESSING
41