GC5018_06 Datasheet, PDF (4/134 Pages) Texas Instruments – 8-CHANNEL WIDEBAND RECEIVER

GC5018
8-CHANNEL WIDEBAND RECEIVER
SLWS169A – MAY 2005 – REVISED NOVEMBER 2005
www.ti.com
Signal input data is clocked into 8-stage FIFOs using a matching external clock signal adcclk_a/b/c/d.
Signal data is clocked out of the FIFO from a gated rxclk (the GC5018 receive section clock). The FIFO
allows arbitrary phase relationship between adcclk_a/b/c/d and rxclk. The frequency relationship is
mandated by the programmed configuration.
The test and noise generator can supply test sequences or add noise to the input signal data. The test
sequences, when combined with the checksum generators, are useful for initial board debug or power-on
self-test.
For applications that require receiver desensitization, the noise generator can add noise to input data
streams.
Many internal chip signals can be routed to the testbus for evaluation and debug purposes. When the
testbus is enabled, the rxin_c and rxin_d ports are driven as digital outputs.
Each of the four outputs to the DDC channels includes a 1 to 64 sample delay line.
VARIABLE
ssel_ddc(2:0)
offset_bin_X
msb_pos_X(2:0)
PROGRAMMING
DESCRIPTION
Selects the sync source for the DDC data input mux and mixer. This sets the sync source for DDC input clock
generation and synchronization for all DDC channels.
Selects offset binary input when set, 2’s complement input when cleared. X={a,b,c,d}
Identifies the connection location of the ADC’s MSB. Programmed values of {0..7} corresponds to msb at {rxin_x_15..
rxin_x_8}. X={a,b,c,d}
3.1.1 Receive FIFO
The receive FIFO consists of an 8 stage memory and 2 counters generating the input write pointer and
output read pointer. When the FIFO receives a sync signal, the input and output pointers are initialized
with a write to read pointer offset of four samples. Input samples from rxin_X (writes) are clocked with the
adcclk_X input clock rising edges, and the input pointer advances on each clock rising edge. Output
samples (reads) and the output pointer are clocked with the rxclk input signal rising edges, divided by the
programmed sample rate loaded into the rate_sel(1:0) control register.
VARIABLE
adc_fifo_bypass
ssel_adc_fifo(2:0)
rate_sel(1:0)
adc_fifo_strap_ab
adc_fifo_strap_cd
PROGRAMMING
DESCRIPTION
When set, bypasses the input FIFOs and input data is latched directly using the rxclk. When cleared, input data is
latched using the adcclk_a/b/c/d inputs.
Selects the sync source for the FIFO state machines. This sync signal initializes the FIFO input and output
pointers.
This selects the FIFO input and output rate; {rxclk, rxclk/2, rxclk/4 or rxclk/8 }. For example, with rxclk at
153.6MHz, set rate_sel to 0, 1, 2 or 3 respectively for adcclk_a/b/c/d 153.6, 76.8, 38.4 or 19.2MHz.
When set, the rxin_a and rxin_b FIFO input and output pointers are synchronized to support complex input
signals.
When set, the rxin_c and rxin_d FIFO input and output pointers are synchronized to support complex input
signals.
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RECEIVE DIGITAL SIGNAL PROCESSING