GC5018_06 Datasheet, PDF (43/134 Pages) Texas Instruments – 8-CHANNEL WIDEBAND RECEIVER

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VARIABLE
par_recv_fsinvl(6:0)
par_recv_clkdiv(6:0)
par_recv_chan(3:0)
par_recv_sync_del(6:0)
par_recv_syncout_del(3:0)
par_recv_rxclk_pol
par_recv_sync_pol
par_recv_ena
ssel_serial(2:0)
gain_mon
tristate(6:3)
GC5018
8-CHANNEL WIDEBAND RECEIVER
SLWS169A – MAY 2005 – REVISED NOVEMBER 2005
PROGRAMMING
DESCRIPTION
rx_sync_out (frame strobe) sync interval. 0 is 1 rxclk cycle and 127 is 128 rxclk cycles.
rxclk_out cycles per IQ channel sample; 1 is full rate, 2 is rxclk/2, etc.
Number channels to be output. 0 is 1 channel, and 15 is 16 channels.
Delays the DDC0 pser sync source to establish the timing of IQ DDC0. Increasing the value delays the
par_sync_out location.
Delays the rx_sync_out position with respect to IQ DDC0. Setting to 0 moves the rx_sync_out pulse one
rxclk_out cycle before the IQ DDC0 word, setting to 1 places it as shown above, lined up with IQ DDC0,
etc.
rxclk_out polarity. Outputs data on falling edges when cleared, rising edges when set.
Parallel interface par_sync_out polarity. 0 is active low, 1 for active high
Parallel TCI110 style interface enabled when set, serial interface enabled when cleared.
DDC channel serial interface sync source selection. All DDCs should be programmed to the same sync
source when using this parallel output interface.
When set, the parallel output data includes 8b I at I(15:8), 8b Q at Q(15:8), 14b AGC gain at I(7:0) and
Q(7:2) and 2b AGC state at Q(1:0).
3-state controls for the rx_sync_out_X and rxout_X_X pins. Pins are in 3-state when the 3-state register
bits are set.
3.2.12 DDC Checksum Generator
The checksum generator is used in conjunction with the input test signal generator to implement a self test
capability.
sync
rxclk
rxout_X_a
rxout_X_b
rxout_X_c
rxout_X_d
checksum ¹⁶
generator
results
register
checksum read−only
results updated on
each sync event
initialized on sync event to “0000 0000 0000 0010”
15
rxout_X_a
rxout_X_b
rxout_X_c
rxout_X_d
14
1312 11
10
9
3
21
0
Figure 3-34. DDC Checksum Generator Block Diagram
The sync for the checksum generator is internally connected to the ddc_counter output.
VARIABLE
ddc_chk_sum(15:0)
PROGRAMMING
DESCRIPTION
Read only DDC channel checksum results
RECEIVE DIGITAL SIGNAL PROCESSING
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