GC5018_06 Datasheet, PDF (113/134 Pages) Texas Instruments – 8-CHANNEL WIDEBAND RECEIVER

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4.4.5.25 PSER_CONFIG1 Register
GC5018
8-CHANNEL WIDEBAND RECEIVER
SLWS169A – MAY 2005 – REVISED NOVEMBER 2005
Register name: PSER_CONFIG1
Page: 0x0%00
where:
% = 2×(DDC channel #)+1
Address: 0x18
BIT 15
unused
pser_recv_fsinvl(6:0)
0
0
0
0
0
0
0
BIT 7
unused
unused
unused
0
0
0
0
pser_recv_bits(4:0)
0
0
0
BIT 8
0
BIT 0
0
pser_recv_fsinvl(6:0) : Receive serial interface frame sync interval in bit clocks.
pser_recv_bits(4:0) : Number of output bits per sample-1; for 18 bits, this is set to {10001}.
4.4.5.26 PSER_CONFIG2 Register
Register name: PSER_CONFIG2
BIT 15
0
pser_recv_clkdiv(3:0)
0
0
BIT 7
pser_recv_8pin
0
pser_recv_alt
0
unused
0
Page: 0x0%00
where:
% = 2×(DDC channel #)+1
unused
0
0
unused
0
unused
0
Address: 0x19
unused
0
unused
0
unused
0
BIT 8
unused
0
BIT 0
pser_recv_fsdel(1:0)
0
0
pser_recv_clkdiv(3:0) : Receive serial interface clock divider rate-1; 0 is full rate and 15 divides the
clock by 16. For example, to run the receive serial interface at 1/4 the GC5018 clock, set
pser_recv_clkdiv(3:0) = 0011.
pser_recv_8pin : When set, 4 pins are used for I and 4 pins for Q in UMTS mode. When cleared, 2 pins
are used for I and 2 pins for Q. This is used in combination with the pser_recv_alt bit. When
this bit is set, it would be set in 2 adjacent DDC channels; one would also set the
pser_recv_alt bit in the adjacent DDC. This will cause the I channel to be serialized on 4 pins
and the Q channel to be serialized on the adjacent channels 4 pins.
pser_recv_alt : When set, this channel's receive serial interface will output the Q data from the adjacent
DDC channel.
pser_recv_fsdel(1:0) : Delay between the receive frame sync output and the MSB of serial data
{3,2,1,0}. This number is in serial output bit times, not rxclk periods.
GC5018 GENERAL CONTROL 113