GC5018_06 Datasheet, PDF (40/134 Pages) Texas Instruments – 8-CHANNEL WIDEBAND RECEIVER

GC5018
8-CHANNEL WIDEBAND RECEIVER
SLWS169A – MAY 2005 – REVISED NOVEMBER 2005
3.2.11.1 Serial Output Interface
sync
clkdiv ⁴
frame
strobe
2
delay
DDC Block
1 UMTS mode channel or
2 CDMA mode channels
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rxout_X_a
rxout_X_b
rxout_X_c
rxout_X_d
CDMA
I ch A
I ch B
Q ch A
Q ch B
Serial Outputs
UMTS
I msb
I msb−1
Q msb
Q msb−1
double length
PFIR UMTS
I msb
I msb−1
I msb−2
I msb−3
rx_sync_out_X
four outputs from
adjacent DDC block
Q msb
Q msb−1
Q msb−2
Q msb−3
Figure 3-30. Serial Output Block Diagram and Output Pins for Each DDC Filter Mode
Each DDC block can be assigned four serial output data pins. These pins are used to transfer
downconverted I/Q baseband data out of the GC5018 for subsequent processing. The usage of these pins
changes depending on how the DDC block is configured.
When the block is configured for two CDMA channels, a pair of serial data pins provides separate I and Q
data output for the two DDC channels. Word size is selectable from 4 to 25 bits with the most significant
bit first.
When the DDC block is configured for a single UMTS channel, even and odd I and Q data drive the four
serial pins separately, most significant bit first.
Four serial pins each for I and Q data can be optionally employed (instead of two for I and two for Q) at
half the output rate. This would most likely be used when two DDC channels (2k and 2k + 1, k= 0 to 5) are
combined to support double-length PFIR filtering (a channel is sacrificed). Formatting for I data is then:
Imsb, Imsb-1, Imsb-2, Imsb-3. Q data formatting is: Qmsb, Qmsb-1, Qmsb-2, Qmsb-3.
The frame strobe signal provided on the rx_sync_out_X pins can be programmed to arrive from 0 to 3 bit
clocks early via a 2 bit control parameter. The frame interval can be programmed from 1 to 63 bits. A
programmable 4-bit clock divider circuit is used to specify the serial bit rate. The clock divider circuit is
synchronized using a sync block discussed later in this document.
Programming the serial port clock divider requires some thought and depends upon the channel’s overall
decimation ratio, frame sync interval, number of output bits, and CDMA-UMTS mode.
In general:
the serial clock divide ratio × the frame sync interval = the total receive decimation
The relationship between the number of serial bits output, clock divide ratio, and overall decimation ratio
is:
CDMA: [overall decimation × (pser_recv_8pin + 1) ] / (pser_recv_clkdiv + 1) > pser_recv_bits + 1
UMTS: 2 × [overall decimation × (pser_recv_8pin + 1) ] / (pser_recv_clkdiv + 1) > pser_recv_bits + 1
where overall decimation = CIC DECIMATION × 2.
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RECEIVE DIGITAL SIGNAL PROCESSING