GC5018_06 Datasheet, PDF (13/134 Pages) Texas Instruments – 8-CHANNEL WIDEBAND RECEIVER

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VARIABLE
slf_tst_ena
rduz_sens_ena
nz_pwr_mask(15:0)
adc_fifo_bypass
ddc_counter(31:0)
ddc_counter_width(7:0)
ssel_ddc_counter(2:0)
self_test_constant(17:0)
self_test_const_ena
GC5018
8-CHANNEL WIDEBAND RECEIVER
SLWS169A – MAY 2005 – REVISED NOVEMBER 2005
PROGRAMMING
DESCRIPTION
When set, the test signal generators replace the rxin_a/b/c/d input signals with internally generated
psuedo random sequences. The fifo_bypass bit must be set when this bit is set.
Enables the LFSR, adding noise to the ADC input data when set.
Selects the power of the noise added to the ADC input data.
When set, the FIFO is essentially bypassed, and the adcclk_a/b/c/d clock input ports are ignored.
32 bit general purpose counter interval
8 bit general purpose counter timeout width pulse
Sync source selection for the general purpose counter
18-bit self test constant value applied to all 4 rxin_a/b/c/d inputs when self_test_const_ena is set.
Enables the self test constant value for rxin_a/b/c/d
3.1.5 Sample Delay Lines
The four sample delay line blocks each consist of a 64 register memory and a state machine. The state
machine uses a counter to control the write (input) pointer, and the programmed read offset register data
to create the read (output) pointer. Programming larger read offset register values increases the effective
delay at a resolution equal to the sample rate.
The read offset registers, delay_line_X, are double buffered. Writes to these registers may occur anytime,
but the actual values used by the circuit will not be updated until a delay line sync event occurs.
VARIABLE
delay_line_X(5:0)
ssel_delay_line_X(2:0)
PROGRAMMING
DESCRIPTION
Read offset into the 64 element memory for each delay line. X= {0,1,2,3}.
Selects the sync source used to update the double buffered delay line register.
3.1.6 Test Bus
When the test bus is enabled, the rxin_c(15:0) and rxin_d(15:0) ports become outputs, and the dvga_c
and dvga_d pins are combined with these pins to allow 36 bit wide signals from the DDC channels and the
receive input interface to be multiplexed to this test output port. Many of these sources can be decimated
to reduce the output sample rates.
RECEIVE DIGITAL SIGNAL PROCESSING
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