GC5018_06 Datasheet, PDF (8/134 Pages) Texas Instruments – 8-CHANNEL WIDEBAND RECEIVER

GC5018
8-CHANNEL WIDEBAND RECEIVER
SLWS169A – MAY 2005 – REVISED NOVEMBER 2005
www.ti.com
The AGC measurement interval timer is a 24-bit timer initialized by a sync after a programmable 8-bit
delay. During the integration interval, the squared input signal is shifted by the programmed value and
accumulated. At the end of the interval time, an update pulse is generated, and the selected 7 bits of the
55-bit accumulated power is upper limit checked and transferred to the power holding register. A
programmable offset is applied, and the following limit check produces a 7 bit address value for the error
map table RAM. The user programmable error map table and following gain shift setting are used to
determine the loop error signal to be added to the 32-bit AGC loop accumulator. The error value is only
added to the loop accumulator once per update. The loop accumulator upper 6 MSBs are used as the
address for the programmable DVGA map table and gain map table. The gain map table address can be
delayed from 0 to 31 clock cycles to align DVGA changes to signal level changes at the output of the
AGC.
The AGC includes four sources for freezing the loop and holding the loop accumulator constant. A general
sync source can be used to directly control the freeze; when the selected sync source is high, the AGC
will be held, and when low, the AGC will operate. A control register bit freezes the AGC in the same
fashion; when the bit is set, the AGC is held, and when cleared, the AGC will operate. A signal level
detector is provided that can be used to automatically freeze the AGC loop in the event of input signal
loss. A programmable signal detection threshold value, number of samples below the signal detection
threshold, and window timer are used to determine when no signal is present. Finally, a programmable
number of AGC updates after sync can be programmed, and the AGC will he held until the next sync
event. Freeze holds the loop accumulator constant, the integrate and dump accumulator constant and the
interval timer constant. When freeze is released, the interval timer will resume counting.
A sync event will always reinitialize the integrate and dump interval timer, and terminate the pending
update to the loop accumulator from the current integrate and dump measurement interval. For example, if
a sync event occurs during an integrate and dump interval, that interval will be terminated without updating
the loop, and the integrate and dump accumulator will be cleared. After the programmed sync delay, a
new interval will start.
The AGC includes a dual threshold clip detect function, using two programmable 16-bit thresholds and
programmable counters. The clip detector will cause immediate loop accumulator updates while the clip
event is active. The 16-bit clip error value is aligned at the MSBs of the loop accumulator. Clip events are
qualified when a programmed number of samples are above the high clip threshold during the
programmable clip window time. For example, a clip event can be defined as 8 samples above the clip
high threshold in a 256 sample window; the clip high threshold, the number of samples above the high clip
threshold and the sample window time are programmable. Once the clip event has occurred, the clip
duration is controlled by the clip low threshold value, clip low samples value and clip low timer. The clip
event is cleared when the number of samples below the low clip threshold exceeds the programmed value
within the clip low timer window. The clip low threshold, number of clip low samples and the clip low
window timer are programmable.
The AGC blocks can be paired together, rxin_a with rxin_b, and rxin_c with rxin_d, to produce a complex
input AGC mode. The clip detector output from the rxin_b/d AGCs is logically OR’ed with the rxin_a/c clip
detect outputs. The squared input function before the integrate and dump and signal level detector is
replaced with a I² + Q² power calculation. The accumulator MSBs from the rxin_a/c AGCs are connected
to the rxin_c/d DVGA map table and gain map table inputs. This arrangement allows the AGCs to operate
in a direct conversion receiver system by controlling the I² + Q² complex signal level.
The highpass filter is a 32 bit accumulator followed by an adjustable shift to control the corner frequency,
a subtractor to remove the accumulated offset and a final limiter to produce a 16 bit result. The highpass
filter function is enabled by setting hp_ena; clearing hp_ena holds the accumulator reset.
8
RECEIVE DIGITAL SIGNAL PROCESSING