GC5018_06 Datasheet, PDF (55/134 Pages) Texas Instruments – 8-CHANNEL WIDEBAND RECEIVER

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4.4.2.2 PAGE Register
GC5018
8-CHANNEL WIDEBAND RECEIVER
SLWS169A – MAY 2005 – REVISED NOVEMBER 2005
Register name: PAGE
BIT 15
unused
unused
0
0
BIT 7
Y(1)
Y(0)
0
0
Address: 0x21
unused
0
Zp
0
0
unused
0
W(2:0)
0
unused
0
0
unused
0
X
0
unused
0
BIT 8
Y(2)
0
BIT 0
unused
0
W(2:0) :
X:
Y(2:0) :
Selects which dual DDC block to address.
The DDC modules are configured as dual DDCs; an even numbered DDC and odd
numbered DDC are contained in each dual DDC module, the X bit selects which DDC gets
address. (DDC0/2/4/6=0, DDC1/3/5/7=1)
W(2:0)
X bit
Selected Block
000
0
DDC0
000
1
DDC1
001
0
DDC2
001
1
DDC3
010
0
DDC4
010
1
DDC5
011
0
DDC6
011
1
DDC7
100
0
Receive AGC0/1 RAMs
101
0
Receive AGC2/3 RAMs
110
0
Receive Input Interface
Within each major block, there are up to 8 different Zones that can be addressed using the Y
bits.
Y(2:0)
000
001
010
011
100
101
110
111
Zp :
DDC Zone
PFIR coeffient lower 2 bits
PFIR coeffient upper 16 bits
CFIR coeffient lower 2 bits
CFIR coeffient upper 16 bits
Control registers
Not assigned
Not assigned
Not assigned
Receive Input Interface Zone
CHIPS control registers
RAGC control registers
Not assigned
Not assigned
Not assigned
Not assigned
Not assigned
Not assigned
Receive AGC RAMs Zone
RAGC0/2 ERRMAP
RAGC0/2 DVGAMAP
RAGC0/2 GAINMAP
Not assigned
RAGC1/3 ERRMAP
RAGC1/3 DVGAMAP
RAGC1/3 GAINMAP
Not assigned
The Zp bit is the MSB of the address word sent to the registers and rams. This bit can be
thought of as an upper/lower selector of the 64 word addressing.
GC5018 GENERAL CONTROL
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