GC5018_06 Datasheet, PDF (34/134 Pages) Texas Instruments – 8-CHANNEL WIDEBAND RECEIVER

GC5018
8-CHANNEL WIDEBAND RECEIVER
SLWS169A – MAY 2005 – REVISED NOVEMBER 2005
www.ti.com
VARIABLE
crastarttap_pfir(4:0)
cdma_mode
mpu_ram_read
pfir_gain(2:0)
double_tap(1:0)
PROGRAMMING
DESCRIPTION
Number of DDC PFIR filter taps is 4x(crastartap+1)
For double length PFIR the number of taps is 8x(crastartap+1)
When set, puts the CFIR & PFIR blocks in CDMA mode.
What set, the PFIR and CFIR coefficient rams are readable via the MPU control interface.
The GC5018 signal path is not operational when this bit is set, it is intended for debug purposes only.
Sets the gain of the PFIR filter.
The range is from 2e^–19 to 2e^–12; “000”= 2e^–19 and “111”= 2e^–12
When set, puts two adjacent DDC (2k and 2k+1, k=0 to 2) in double length (from 64 to128 tap) UMTS
mode.
Set to “00” for normal mode.
In double tap mode, data out of the last PFIR ram in the main DDC (DDC0, DDC2, DDC4 or DDC6) is
sent to the adjacent secondary DDC (DDC1, DDC3, DDC5 or DDC7) PFIR as input thus forming a
128-tap delay line. Data received from the adjacent PFIR summers is added into the Main DDC’s PFIR
sum to form the final output.
When using double tap mode, set double_tap to “10” for the main DDC, and to “01” for the secondary
DDC.
When in double tap mode, the first half of the coefficients should be loaded into the main DDC (DDC0,
DDC2, DDC4 or DDC6), the remaining coefficients are loaded into the secondary DDC (DDC1, DDC3,
DDC5 or DDC7).
In double tap mode, the main DDC must be turned on (ddc_ena=1), and the secondary DDC must be
turned off (ddc_ena=0).
The PFIR filter’s 18 bit coefficients are loaded in four 16 word memories.
Note: PFIR filter coefficients are shared between A and B channels of a DDC block when in CDMA mode.
3.2.9 DDC RMS Power Meter
18
I
18
Q
36
37 _55−bit
Integrator
36
55−bit ^{RMS power}
Register
clear
transfer
sync
8−bit
sync delay
counter
8
18−bit
interval
counter
8
18−bit
integration
counter
16
interrupt
delay
(in samples)
interval
(in 1024 sample
increments)
integration
(in 4 sample
increments)
Figure 3-26. DDC RMS Power Meter Block Diagram
34
RECEIVE DIGITAL SIGNAL PROCESSING