GC5018_06 Datasheet, PDF (3/134 Pages) Texas Instruments – 8-CHANNEL WIDEBAND RECEIVER

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GC5018
8-CHANNEL WIDEBAND RECEIVER
SLWS169A – MAY 2005 – REVISED NOVEMBER 2005
Each DDC block selects one of the four channels (or 2 for complex input data) from the rx_distribution bus
and then performs downconversion tuning, programmable delay, channel filtering with decimation, power
measurement, fixed gain adjust and/or automatic gain control. Each DDC block can support 1 UMTS
channel, 2 CDMA channels or 2 TD-SCDMA channels. An optional mode permits stacking two DDC
blocks in UMTS mode to provide double-length final pulse shaping filtering.
Tuned, filtered, and decimated signal data is output in bit serial or parallel format.
3.1 Receive Input Interface
dvga_a
rxin _a 16
test & noise ¹⁶
signal
generator
to testbus
6
FIFO ¹⁶
dual real or
single complex
Power Meter
rxin _b
16
test & noise ¹⁶
signal
generator
FIFO ¹⁶
dvga_b
6
dvga_c
rxin _c 16
test & noise ¹⁶
signal
generator
test bus select
and decimation
6
FIFO ¹⁶
testbus
sources
dual real or
single complex
Power Meter
rxin _d
16
test & noise ¹⁶
signal
generator
FIFO ¹⁶
dvga_d
6
dual real or
single complex
AGC
dual real or
single complex
AGC
18
1 to 64
sample
delay
line
delay_a ₁₈
1 to 64
sample
delay
line
delay_b
18
1 to 64
sample
delay
line
delay_c ₁₈
1 to 64
sample
delay
line
rx_distribution
bus to DDC
channels
Figure 3-1. Receive Data Input Interface
delay_d
The GC5018’s receive input data interface accepts data from two sources:
• Signal data presented at the four 16-bit digital data input ports.
• A LFSR test signal generator allows the GC5018 to be tested using a known repetitive data sequence.
Signal data can be provided in binary or 2’s complement form. The location of the ADC’s MSB can be
programmed to allow for additional AGC headroom if desired. For example, a 14-bit ADC may be
connected with the MSBs aligned, or shifted down to allow the AGC additional gain range before clipping
the signal.
Signal data can be accepted at rates up to rxclk in UMTS mode for either 8 normal channels or 4 double
length final pulse shaping filter channels. In CDMA mode the maximum input rate is rxclk for real inputs, or
rxclk/2 for complex inputs. For maximum filter performance, higher clock rates generally allow longer
filters.
Complex signal data is input with I data driving one input port and Q data driving another. This means that
there are only two signal data ports available when using complex input mode. The mapping of I and Q
data onto the four input ports is programmable.
RECEIVE DIGITAL SIGNAL PROCESSING
3