GC5018_06 Datasheet, PDF (23/134 Pages) Texas Instruments – 8-CHANNEL WIDEBAND RECEIVER

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GC5018
8-CHANNEL WIDEBAND RECEIVER
SLWS169A – MAY 2005 – REVISED NOVEMBER 2005
The CIC filter exhibits a droop across its frequency response. The following CFIR filter compensates for
the CIC droop with a gradually rising frequency response. It is also possible to compensate for CIC droop
in the PFIR filter.
The gain of the receive CIC filter is:
Ncic⁶ x 2^{(number of stages where M=2)} x 2^{(–36+RCIC_SHIFT)} where RCIC_SHIFT is 0 to 31.
There is no rollover protection internal to the CIC or at the final round so the user must guarantee no
sample exceeds full scale prior to rounding. For practical purposes this means the CIC gain can only
compensate for peak gain less than one or must be less than or equal to one. A fixed gain of +12 dB at
the output of the CIC can also be programmed.
VARIABLE
cic_decim(4:0)
cic_scale_a(4:0)
cic_scale_b(4:0)
cic_gain_ddc
cic_m2_ena_a(5:0)
cic_m2_ena_b (5:0)
cic_bypass
ssel_cic(2:0)
PROGRAMMING
DESCRIPTION
The CIC decimation ratio (4 to 32). The ratio is cic_decim + 1. This ratio applies to both A and B channels of
the DDC block in CDMA mode.
The shift value for the A channel. A value of 0 is no shift, each increment in value increases the amplitude of
the shifter output by a factor of 2.
The shift value for the B channel. A value of 0 is no shift, each increment in value increases the amplitude of
the shifter output by a factor of 2.
When asserted, adds a gain of 12 dB at the CIC output.
Sets the differential delay value M for each of the CIC subtractor stages for the UMTS or CDMA mode A
channel.
Sets the differential delay value M for each of the CIC subtractor stages for the CDMA mode B channel.
Bypasses the CIC filter when set, for factory testing.
Sets syncing (1 of 8 sources) for the CIC decimation moment.
3.2.7 DDC Compensating FIR Filter (CFIR)
The receive compensating FIR filter (CFIR) decimates the output of the CIC filter by a fixed factor of two.
Filter coefficient size, input data size, and output data size are 18 bits. The CFIR length can be
programmed. This permits “turning off” taps and saving power if shorter filters are appropriate (the CFIR
power dissipation is proportional to its length).
The filter is organized in two partial filter blocks, each containing a data RAM, a coefficient RAM and a
dual multiplier, a common state machine and output accumulator.
RECEIVE DIGITAL SIGNAL PROCESSING
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