GC5018_06 Datasheet, PDF (107/134 Pages) Texas Instruments – 8-CHANNEL WIDEBAND RECEIVER

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4.4.5.15 CONFIG1 Register
GC5018
8-CHANNEL WIDEBAND RECEIVER
SLWS169A – MAY 2005 – REVISED NOVEMBER 2005
Register name: CONFIG1
BIT 15
dither_ena
0
BIT 7
unused
0
dither_mask(1:0)
0
0
unused
0
unused
0
Page: 0x0%00
where:
% = 2×(DDC channel #)+1
pmeter_ sync_
disable
0
ddc_ena
0
unused
0
unused
0
Address: 0x0E
muxed _data
mixer_gain
BIT 8
mpu_ram_read
0
0
zero_ qsample
0
mux_pos
0
0
BIT 0
mux_factor
0
dither_ena : This bit controls whether dither is turned on(1) or off(0).
dither_mask(1) : This bit controls the MASKing of the dither word’s MSB. (1= MASKed, 0=used in dither
word)
dither_mask(0) : This bit controls the MASKing of the dither word’s MSB-1. (1= MASKed, 0=used in
dither word)
pmeter_sync_disable : Turns off the sync to the channel power meter. This can be used to individually
turn off syncs to a channels power meter while still having syncs to other power meters
available.
ddc_ena : When set this turns on the DDC. When cleared, the clocks to this block are turned off. For
the DDC blocks used as the second half in the long PFIR configuration, this bit should be
cleared.
muxed_data : When asserted the DDC mux block assumes that multiple channels are muxed together on
one input data stream. For factory use only.
For a 2X muxed stream it would look like: Sa0, Sb0, Sa1, Sb1, Sa2, Sb2 …. etc...
mixer_gain : Adds a fixed 6 dB of gain to the mixer output(before round and limiting) when asserted.
mpu_ram_read : (TESTING PURPOSES) Allows the coefficient RAMs in the PFIR/CFIR to be read out
the mpu data bus. Unfortunately, this cannot be done during normal operation and must be
done when the state of the output data is not important. THIS BIT MUST ONLY BE SET
DURING THE MPU READ OPERATION AND MUST BE CLEARED FOR NORMAL DDC
OPERATION.
zero_qsample : When asserted, the Q sample into the mixer is held to zero. For UMTS mode at any input
rate, and CDMA mode with input rates of rxclk/2 or lower, this bit must be set for real only
input data mode (also for muxed input data stream modes). For real only inputs at the full
rxclk rate in CDMA mode, the remix_only bit must be set in the DDCCONFIG1 register.
mux_pos : These bits set the position for selection in the muxed data stream. This value must be less
than or equal to the mux_factor bits.
mux_factor : These two bits set the number of channels in the data stream. 0=1 stream, 1=2 streams.
The ch_rate_sel bits for the DDC should be programmed to rxclk/2 for the 2 streams mode.
GC5018 GENERAL CONTROL 107