LSM6DSL Datasheet, PDF (56/113 Pages) STMicroelectronics – iNEMO inertial module: always-on 3D accelerometer and 3D gyroscope

Register description
LSM6DSL
9.8
FIFO_CTRL5 (0Ah)
FIFO control register (r/w).
Table 38. FIFO_CTRL5 register
0⁽¹⁾
ODR_ ODR_ ODR_ ODR_
FIFO_3 FIFO_2 FIFO_1 FIFO_0
FIFO_
MODE_2
FIFO_
MODE_1
FIFO_
MODE_0
1. This bit must be set to ‘0’ for the correct operation of the device.
Table 39. FIFO_CTRL5 register description
ODR_FIFO_[3:0]
FIFO ODR selection, setting FIFO_MODE also. Default: 0000
For the configuration setting, refer to Table 40.
FIFO_MODE_[2:0] ^{FIFO mode selection bits, setting ODR_FIFO also. Default value: 000}
For the configuration setting, refer to Table 41.
ODR_FIFO_[3:0]
Table 40. FIFO ODR selection
Configuration⁽¹⁾
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
FIFO disabled
FIFO ODR is set to 12.5 Hz
FIFO ODR is set to 26 Hz
FIFO ODR is set to 52 Hz
FIFO ODR is set to 104 Hz
FIFO ODR is set to 208 Hz
FIFO ODR is set to 416 Hz
FIFO ODR is set to 833 Hz
FIFO ODR is set to 1.66 kHz
FIFO ODR is set to 3.33 kHz
FIFO ODR is set to 6.66 kHz
1. If the device is working at an ODR slower than the one selected, FIFO ODR is limited to that ODR value.
Moreover, these bits are effective if both the DATA_VALID_SEL_FIFO bit of MASTER_CONFIG (1Ah) and
the TIMER_PEDO_FIFO_DRDY bit of FIFO_CTRL2 (07h) are set to 0.
Table 41. FIFO mode selection
FIFO_MODE_[2:0]
Configuration mode
000
Bypass mode. FIFO disabled.
001
FIFO mode. Stops collecting data when FIFO is full.
010
Reserved
011
Continuous mode until trigger is deasserted, then FIFO mode.
100
Bypass mode until trigger is deasserted, then Continuous mode.
101
Reserved
110
Continuous mode. If the FIFO is full, the new sample overwrites the older one.
111
Reserved
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