LSM6DSL Datasheet, PDF (38/113 Pages) STMicroelectronics – iNEMO inertial module: always-on 3D accelerometer and 3D gyroscope

Digital interfaces
LSM6DSL
The slave address is completed with a Read/Write bit. If the bit is ‘1’ (Read), a repeated
START (SR) condition must be issued after the two sub-address bytes; if the bit is ‘0’ (Write)
the master will transmit to the slave with direction unchanged. Table 12 explains how the
SAD+Read/Write bit pattern is composed, listing all the possible configurations.
Command
Read
Write
Read
Write
SAD[6:1]
110101
110101
110101
110101
Table 12. SAD+Read/Write patterns
SAD[0] = SA0
R/W
SAD+R/W
0
1
11010101 (D5h)
0
0
11010100 (D4h)
1
1
11010111 (D7h)
1
0
11010110 (D6h)
Table 13. Transfer when master is writing one byte to slave
Master
ST
SAD + W
SUB
DATA
SP
Slave
SAK
SAK
SAK
Table 14. Transfer when master is writing multiple bytes to slave
Master ST SAD + W
SUB
DATA
DATA
SP
Slave
SAK
SAK
SAK
SAK
Table 15. Transfer when master is receiving (reading) one byte of data from slave
Master ST SAD + W
SUB
SR SAD + R
NMAK SP
Slave
SAK
SAK
SAK DATA
Table 16. Transfer when master is receiving (reading) multiple bytes of data from slave
Master ST SAD+W
SUB
SR SAD+R
MAK
MAK
NMAK SP
Slave
SAK
SAK
SAK DATA
DAT
A
DATA
Data are transmitted in byte format (DATA). Each data transfer contains 8 bits. The number
of bytes transferred per transfer is unlimited. Data is transferred with the Most Significant bit
(MSb) first. If a receiver can’t receive another complete byte of data until it has performed
some other function, it can hold the clock line, SCL LOW to force the transmitter into a wait
state. Data transfer only continues when the receiver is ready for another byte and releases
the data line. If a slave receiver doesn’t acknowledge the slave address (i.e. it is not able to
receive because it is performing some real-time function) the data line must be left HIGH by
the slave. The master can then abort the transfer. A LOW to HIGH transition on the SDA line
while the SCL line is HIGH is defined as a STOP condition. Each data transfer must be
terminated by the generation of a STOP (SP) condition.
In the presented communication format MAK is Master acknowledge and NMAK is No
Master Acknowledge.
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