HD64F36024FX Datasheet, PDF (99/386 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 6 Power-Down Modes
6.1.2 System Control Register 2 (SYSCR2)
SYSCR2 controls the power-down modes, as well as SYSCR1.
Initial
Bit
Bit Name Value R/W Description
7
SMSEL 0
R/W Sleep Mode Selection
This bit selects the mode to transit after the execution of
a SLEEP instruction, as well as bit SSBY of SYSCR1.
For details, see table 6.2.
6

0

Reserved
This bit is always read as 0.
5
DTON
0
R/W Direct Transfer on Flag
This bit selects the mode to transit after the execution of
a SLEEP instruction, as well as bit SSBY of SYSCR1.
For details, see table 6.2.
4
MA2
3
MA1
2
MA0
1, 0 
0
0
0
All 0
R/W
R/W
R/W

Active Mode Clock Select 2 to 0
These bits select the operating clock frequency in active
and sleep modes. The operating clock frequency
changes to the set frequency after the SLEEP instruction
is executed.
0XX: φ_OSC
100: φ_OSC/8
101: φ_OSC/16
110: φ_OSC/32
111: φ_OSC/64
Reserved
These bits are always read as 0.
Legend: X : Don't care.
Rev. 4.00 Sep. 23, 2005 Page 71 of 354
REJ09B0025-0400