HD64F36024FX Datasheet, PDF (238/386 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 13 Serial Communication Interface 3 (SCI3)
13.6.2 Multiprocessor Serial Data Reception
Figure 13.17 shows a sample flowchart for multiprocessor serial data reception. If the MPIE bit in
SCR3 is set to 1, data is skipped until data with a 1 multiprocessor bit is sent. On receiving data
with a 1 multiprocessor bit, the receive data is transferred to RDR. An RXI interrupt request is
generated at this time. All other SCI3 operations are the same as those in asynchronous mode.
Figure 13.18 shows an example of SCI3 operation for multiprocessor format reception.
Rev. 4.00 Sep. 23, 2005 Page 210 of 354
REJ09B0025-0400