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HD64F36024FX Datasheet, PDF (118/386 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents | |||
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Section 7 ROM
Erase start
SWE bit â 1
Wait 1 µs
nâ1
Set EBR1
Enable WDT
ESU bit â 1
Wait 100 µs
E bit â 1
Wait 10 ms
E bit â 0
Wait 10 µs
ESU bit â 10
10 µs
Disable WDT
EV bit â 1
Wait 20 µs
Set block start address as verify address
H'FF dummy write to verify address
Wait 2 µs
*
Read verify data
Increment address
No
No
Verify data + all 1s ?
Yes
Last address of block ?
Yes
EV bit â 0
Wait 4 µs
EV bit â 0
Wait 4µs
nân+1
No
All erase block erased ?
Yes
Yes
SWE bit â 0
Wait 100 µs
n â¤100 ?
Yes
No
SWE bit â 0
Wait 100 µs
End of erasing
Erase failure
Note: * The RTS instruction must not be used during a period between dummy writing of H'FF to a verify address and verify data reading.
Figure 7.4 Erase/Erase-Verify Flowchart
Rev. 4.00 Sep. 23, 2005 Page 90 of 354
REJ09B0025-0400
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