HD64F36024FX Datasheet, PDF (268/386 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 17 List of Registers
17.1 Register Addresses (Address Order)
The data bus width indicates the numbers of bits by which the register is accessed.
The number of access states indicates the number of states based on the specified reference clock.
Register Name
Serial mode register_3
Bit rate register_3
Serial control register 3_3
Transmit data register_3
Serial status register_3
Receive data register_3

Abbre-
viation
SMR_3
BRR_3
SCR3_3
TDR_3
SSR_3
RDR_3

SCI3_3 module control register SMCR
Low-voltage-detection control
register
LVDCR
Low-voltage-detection status
register
LVDSR
Serial mode register_2
SMR_2
Bit rate register_2
BRR_2
Serial control register 3_2
SCR3_2
Transmit data register_2
TDR_2
Serial status register_2
SSR_2
Receive data register_2
RDR_2
Timer mode register W
TMRW
Timer control register W
TCRW
Timer interrupt enable register W TIERW
Timer status register W
TSRW
Timer I/O control register 0
TIOR0
Timer I/O control register 1
TIOR1
Timer counter
TCNT
General register A
GRA
Module
Bit No Address Name
8
H'F600 SCI3_3
8
H'F601 SCI3_3
8
H'F602 SCI3_3
8
H'F603 SCI3_3
8
H'F604 SCI3_3
8
H'F605 SCI3_3

H'F606, SCI3_3
H'F607
8
H'F608 SCI3_3
8
H'F730 LVDC*¹
Data Bus Access
Width State
8
3
8
3
8
3
8
3
8
3
8
3


8
3
8
2
8
H'F731 LVDC*¹ 8
2
8
H'F740 SCI3_2 8
3
8
H'F741 SCI3_2 8
3
8
H'F742 SCI3_2 8
3
8
H'F743 SCI3_2 8
3
8
H'F744 SCI3_2 8
3
8
H'F745 SCI3_2 8
3
8
H'FF80 Timer W 8
2
8
H'FF81 Timer W 8
2
8
H'FF82 Timer W 8
2
8
H'FF83 Timer W 8
2
8
H'FF84 Timer W 8
2
8
H'FF85 Timer W 8
2
16
H'FF86 Timer W 16*²
2
16
H'FF88 Timer W 16*²
2
Rev. 4.00 Sep. 23, 2005 Page 240 of 354
REJ09B0025-0400