HD64F36024FX Datasheet, PDF (230/386 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 13 Serial Communication Interface 3 (SCI3)
Serial
clock
Serial
data
TDRE
TEND
Bit 0 Bit 1
1 frame
Bit 7
Bit 0
Bit 1
Bit 6
Bit 7
1 frame
LSI
TXI interrupt
operation request
generated
User
processing
TDRE flag
cleared
to 0
Data written
to TDR
TXI interrupt request generated
TEI interrupt request
generated
Figure 13.10 Example of SCI3 Transmission in Clocked Synchronous Mode
Start transmission
[1] Read SSR and check that the TDRE flag is
set to 1, then write transmit data to TDR.
[1]
Read TDRE flag in SSR
When data is written to TDR, the TDRE flag
is automatically cleared to 0 and clocks are
output to start the data transmission.
TDRE = 1
No
[2] To continue serial transmission, be sure to
read 1 from the TDRE flag to confirm that
writing is possible, then write data to TDR.
Yes
When data is written to TDR, the TDRE flag
is automatically cleared to 0.
Write transmit data to TDR
Yes
[2]
All data transmitted?
No
Read TEND flag in SSR
No
TEND = 1
Yes
Clear TE bit in SCR3 to 0
<End>
Figure 13.11 Sample Serial Transmission Flowchart (Clocked Synchronous Mode)
Rev. 4.00 Sep. 23, 2005 Page 202 of 354
REJ09B0025-0400