HD64F36024FX Datasheet, PDF (149/386 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 10 Timer V
10.3.3 Timer Control Register V0 (TCRV0)
TCRV0 selects the input clock signals of TCNTV, specifies the clearing conditions of TCNTV,
and controls each interrupt request.
Initial
Bit
Bit Name Value R/W Description
7
CMIEB 0
R/W Compare Match Interrupt Enable B
When this bit is set to 1, interrupt request from the CMFB
bit in TCSRV is enabled.
6
CMIEA 0
R/W Compare Match Interrupt Enable A
When this bit is set to 1, interrupt request from the CMFA
bit in TCSRV is enabled.
5
OVIE
0
R/W Timer Overflow Interrupt Enable
When this bit is set to 1, interrupt request from the OVF
bit in TCSRV is enabled.
4
CCLR1 0
R/W Counter Clear 1 and 0
3
CCLR0 0
R/W These bits specify the clearing conditions of TCNTV.
00: Clearing is disabled
01: Cleared by compare match A
10: Cleared by compare match B
11: Cleared on the rising edge of the TMRIV pin. The
operation of TCNTV after clearing depends on TRGE
in TCRV1.
2
CKS2
0
R/W Clock Select 2 to 0
1
CKS1
0
0
CKS0
0
R/W These bits select clock signals to input to TCNTV and the
R/W ^{counting condition in combination with ICKS0 in TCRV1.}
Refer to table 10.2.
Rev. 4.00 Sep. 23, 2005 Page 121 of 354
REJ09B0025-0400