HD64F36024FX Datasheet, PDF (75/386 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 3 Exception Handling
3.2 Register Descriptions
Interrupts are controlled by the following registers.
• Interrupt edge select register 1 (IEGR1)
• Interrupt edge select register 2 (IEGR2)
• Interrupt enable register 1 (IENR1)
• Interrupt flag register 1 (IRR1)
• Wakeup interrupt flag register (IWPR)
3.2.1 Interrupt Edge Select Register 1 (IEGR1)
IEGR1 selects the direction of an edge that generates interrupt requests of pins and IRQ3 and
IRQ0.
Initial
Bit
Bit Name Value
7

0
6 to 4 
All 1
3
IEG3
0
2, 1 
All 0
0
IEG0
0
R/W
−

R/W

R/W
Description
Reserved
This bit is always read as 0.
Reserved
These bits are always read as 1.
IRQ3 Edge Select
0: Falling edge of IRQ3 pin input is detected
1: Rising edge of IRQ3 pin input is detected
Reserved
These bits are always read as 0.
IRQ0 Edge Select
0: Falling edge of IRQ0 pin input is detected
1: Rising edge of IRQ0 pin input is detected
Rev. 4.00 Sep. 23, 2005 Page 47 of 354
REJ09B0025-0400