HD64F36024FX Datasheet, PDF (253/386 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Table 14.3 A/D Conversion Time (Single Mode)
Item
Symbol
Min
A/D conversion start delay t_D
6
Input sampling time
t
—
SPL
A/D conversion time
t
131
CONV
Note: All values represent the number of states.
CKS = 0
Typ Max
—
9
31
—
—
134
Section 14 A/D Converter
CKS = 1
Min Typ Max
4
—
5
—
15
—
69
—
70
14.4.4 External Trigger Input Timing
A/D conversion can also be started by an external trigger input. When the TRGE bit is set to 1 in
ADCR, external trigger input is enabled at the ADTRG pin. A falling edge at the ADTRG input
pin sets the ADST bit to 1 in ADCSR, starting A/D conversion. Other operations, in both single
and scan modes, are the same as when the bit ADST has been set to 1 by software. Figure 14.3
shows the timing.
ø
ADTRG
Internal trigger signal
ADST
A/D conversion
Figure 14.3 External Trigger Input Timing
Rev. 4.00 Sep. 23, 2005 Page 225 of 354
REJ09B0025-0400