HD64F36024FX Datasheet, PDF (67/386 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 2 CPU
(1) Bit manipulation for two registers assigned to the same address
Example: Bit manipulation for the timer load register and timer counter
(Applicable for timer B and timer C, not for the group of this LSI.)
Figure 2.13 shows an example of a timer in which two timer registers are assigned to the same
address. When a bit manipulation instruction accesses the timer load register and timer counter of
a reloadable timer, since these two registers share the same address, the following operations takes
place.
1. Data is read in byte units.
2. The CPU sets or resets the bit to be manipulated with the bit manipulation instruction.
3. The written data is written again in byte units to the timer load register.
The timer is counting, so the value read is not necessarily the same as the value in the timer load
register. As a result, bits other than the intended bit in the timer counter may be modified and the
modified value may be written to the timer load register.
Count clock
Timer counter
Reload
Timer load register
Read
Write
Internal bus
Figure 2.13 Example of Timer Configuration with Two Registers Allocated to
Same Address
Rev. 4.00 Sep. 23, 2005 Page 39 of 354
REJ09B0025-0400