HD64F36024FX Datasheet, PDF (189/386 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 11 Timer W
11.5.5 Buffer Operation Timing
Figures 11.19 and 11.20 show the buffer operation timing.
φ
Compare
match signal
TCNT
N
N+1
GRC, GRD
M
GRA, GRB
M
Figure 11.19 Buffer Operation Timing (Compare Match)
φ
Input capture
signal
TCNT
GRA, GRB
N
N+1
M
N
N+1
GRC, GRD
M
N
Figure 11.20 Buffer Operation Timing (Input Capture)
11.5.6 Timing of IMFA to IMFD Flag Setting at Compare Match
If a general register (GRA, GRB, GRC, or GRD) is used as an output compare register, the
corresponding IMFA, IMFB, IMFC, or IMFD flag is set to 1 when TCNT matches the general
register.
The compare match signal is generated in the last state in which the values match (when TCNT is
updated from the matching count to the next count). Therefore, when TCNT matches a general
register, the compare match signal is generated only after the next TCNT clock pulse is input.
Rev. 4.00 Sep. 23, 2005 Page 161 of 354
REJ09B0025-0400