HD64F36024FX Datasheet, PDF (250/386 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 14 A/D Converter
Initial
Bit Bit Name Value R/W
2
CH2
0
R/W
1
CH1
0
R/W
0
CH0
0
R/W
Legend X: Don't care.
Description
Channel Select 0 to 2
Select analog input channels.
When SCAN = 0
When SCAN = 1
X00: AN0
X00: AN0
X01: AN1
X01: AN0 to AN1
X10: AN2
X10: AN0 to AN2
X11: AN3
X11: AN0 to AN3
14.3.3 A/D Control Register (ADCR)
ADCR enables A/D conversion started by an external trigger signal.
Initial
Bit Bit Name Value R/W
7
TRGE
0
R/W
6 to 1 —
0
—
All 1 —
0
R/W
Description
Trigger Enable
A/D conversion is started at the falling edge and the rising
edge of the external trigger signal (ADTRG) when this bit
is set to 1.
The selection between the falling edge and rising edge of
the external trigger pin (ADTRG) conforms to the WPEG5
bit in the interrupt edge select register 2 (IEGR2)
Reserved
These bits are always read as 1.
Reserved
Do not set this bit to 1, though the bit is readable/writable.
Rev. 4.00 Sep. 23, 2005 Page 222 of 354
REJ09B0025-0400