HD64F36024FX Datasheet, PDF (212/386 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 13 Serial Communication Interface 3 (SCI3)
13.3.8 Bit Rate Register (BRR)
BRR is an 8-bit register that adjusts the bit rate. The initial value of BRR is H'FF. Table 13.3
shows the relationship between the N setting in BRR and the n setting in bits CKS1 and CKS0 of
SMR in asynchronous mode. Table 13.4 shows the maximum bit rate for each frequency in
asynchronous mode. The values shown in both tables 13.3 and 13.4 are values in active (high-
speed) mode. Table 13.5 shows the relationship between the N setting in BRR and the n setting in
bits CKS1 and CKS0 of SMR in clocked synchronous mode. The values shown in table 13.5 are
values in active (high-speed) mode. The N setting in BRR and error for other operating
frequencies and bit rates can be obtained by the following formulas:
[Asynchronous Mode]
N=
φ
64 × 2^2n–1 × B
× 10⁶ – 1
Error
(%)
=

_(N
+
1)
φ
×
×
B
10⁶
× 64
×
2^2n–1
–1
× 100
[Clocked Synchronous Mode]
N=
φ
8 × 2^2n–1 × B
× 10⁶ – 1
[Legend]
B: Bit rate (bit/s)
N: BRR setting for baud rate generator (0 ≤ N ≤ 255)
φ: Operating frequency (MHz)
n: CSK1 and CSK0 settings in SMR (0 ≤ n ≤ 3)
Rev. 4.00 Sep. 23, 2005 Page 184 of 354
REJ09B0025-0400