HD64F36024FX Datasheet, PDF (183/386 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 11 Timer W
Figure 11.11 shows an example of buffer operation when the FTIOB pin is set to PWM mode and
GRD is set as the buffer register for GRB. TCNT is cleared by compare match A, and FTIOB
outputs 1 at compare match B and 0 at compare match A.
Due to the buffer operation, the FTIOB output level changes and the value of buffer register GRD
is transferred to GRB whenever compare match B occurs. This procedure is repeated every time
compare match B occurs.
TCNT value
GRA
GRB
H'0200
H'0000
GRD H'0200
H'0450
H'0450
H'0520
H'0520
Time
GRB
H'0200
H'0450
H'0520
FTIOB
Figure 11.11 Buffer Operation Example (Output Compare)
Rev. 4.00 Sep. 23, 2005 Page 155 of 354
REJ09B0025-0400