HD64F36024FX Datasheet, PDF (188/386 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 11 Timer W
11.5.3 Input Capture Timing
Input capture on the rising edge, falling edge, or both edges can be selected through settings in
TIOR0 and TIOR1. Figure 11.17 shows the timing when the falling edge is selected. The pulse
width of the input capture signal must be at least two system clock (φ) cycles; shorter pulses will
not be detected correctly.
ø
Input capture
input
Input capture
signal
TCNT
N–1
N
N+1
N+2
GRA to GRD
N
Figure 11.17 Input Capture Input Signal Timing
11.5.4 Timing of Counter Clearing by Compare Match
Figure 11.18 shows the timing when the counter is cleared by compare match A. When the GRA
value is N, the counter counts from 0 to N, and its cycle is N + 1.
φ
Compare
match signal
TCNT
N
H'0000
GRA
N
Figure 11.18 Timing of Counter Clearing by Compare Match
Rev. 4.00 Sep. 23, 2005 Page 160 of 354
REJ09B0025-0400