HD64F36024FX Datasheet, PDF (190/386 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 11 Timer W
Figure 11.21 shows the timing of the IMFA to IMFD flag setting at compare match.
φ
TCNT input
clock
TCNT
N
N+1
GRA to GRD
N
Compare
match signal
IMFA to IMFD
IRRTW
Figure 11.21 Timing of IMFA to IMFD Flag Setting at Compare Match
11.5.7 Timing of IMFA to IMFD Setting at Input Capture
If a general register (GRA, GRB, GRC, or GRD) is used as an input capture register, the
corresponding IMFA, IMFB, IMFC, or IMFD flag is set to 1 when an input capture occurs. Figure
11.22 shows the timing of the IMFA to IMFD flag setting at input capture.
φ
Input capture
signal
TCNT
N
GRA to GRD
N
IMFA to IMFD
IRRTW
Figure 11.22 Timing of IMFA to IMFD Flag Setting at Input Capture
Rev. 4.00 Sep. 23, 2005 Page 162 of 354
REJ09B0025-0400