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| HD64F36024FX Datasheet, PDF (31/386 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents | |||
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1.2 Internal Block Diagram
Section 1 Overview
P17/IRQ3/TRGV
P16
P15
P14/IRQ0
P12/SCK3_3*2
P11
P10
P22/TXD
P21/RXD
P20/SCK3
P57/TXD_3*2
P56/RXD_3*2
P55/WKP5/ADTRG
P54/WKP4
P53/WKP3
P52/WKP2
P51/WKP1
P50/WKP0
System
clock
generator
CPU
H8/300H
Data bus (lower)
ROM
RAM
SCI3
Timer W
SCI3_2
Timer V
SCI3_3*1
A/D
converter
Watchdog
timer
Port B
E10T_0*3
E10T_1*3
E10T_2*3
P76/TMOV
P75/TMCIV
P74/TMRIV
P73
P72/TXD_2
P71/RXD_2
P70/SCK3_2
P84/FTIOD
P83/FTIOC
P82/FTIOB
P81/FTIOA
P80/FTCI
Notes: 1. The SCI3_3 function is incorporated in the H8/36024.
2. Since the SCI3_3 function is not incorporated in the H8/36014, the SCK3_3, RXD_3, and TXD_3 pins are not multiplexed.
3. Can also be used for the E7 or E8 emulator.
Figure 1.1 Internal Block Diagram
Rev. 4.00 Sep. 23, 2005 Page 3 of 354
REJ09B0025-0400
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